[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.49 -> 1.50
---
Log message:

added sign extend for boolean

---
Diffs of the changes:  (+5 -3)

 AlphaISelPattern.cpp |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.49 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.50
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.49	Thu Feb 10 14:10:38 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sat Feb 12 13:35:12 2005
@@ -56,9 +56,6 @@
       setOperationAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
       setOperationAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
 
-      //what is the sign expansion of 1? 1 or -1?
-      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 
-
       setOperationAction(ISD::SREM             , MVT::f32  , Expand);
       setOperationAction(ISD::SREM             , MVT::f64  , Expand);
 
@@ -959,6 +956,11 @@
       case MVT::i8:
         BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
         break;
+      case MVT::i1:
+        Tmp2 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
+        BuildMI(BB, Alpha::SUB, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
+        break;
       }
       return Result;
     }