[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp AlphaInstrInfo.td AlphaRegisterInfo.cpp AlphaInstrBuilder.h
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Sat Jan 29 07:42:22 PST 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.16 -> 1.17
AlphaInstrInfo.td updated: 1.8 -> 1.9
AlphaRegisterInfo.cpp updated: 1.4 -> 1.5
AlphaInstrBuilder.h (r1.1) removed
---
Log message:
first step towards a correct and complete stack. also add some forms for things that were getting stuck in the nightly tester.
---
Diffs of the changes: (+78 -12)
AlphaISelPattern.cpp | 82 +++++++++++++++++++++++++++++++++++++++++++++-----
AlphaInstrInfo.td | 4 +-
AlphaRegisterInfo.cpp | 4 +-
3 files changed, 78 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.16 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.17
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.16 Fri Jan 28 17:17:54 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Sat Jan 29 09:42:07 2005
@@ -294,6 +294,24 @@
default:
Node->dump();
assert(0 && "Node not handled!\n");
+
+ case ISD::CopyFromReg:
+ {
+ // Make sure we generate both values.
+ if (Result != notIn)
+ ExprMap[N.getValue(1)] = notIn; // Generate the token
+ else
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+
+ SDOperand Chain = N.getOperand(0);
+
+ Select(Chain);
+ unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
+ //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
+ BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
+ return Result;
+ }
+
case ISD::LOAD:
{
// Make sure we generate both values.
@@ -346,16 +364,57 @@
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
- case ISD::SINT_TO_FP:
+ case ISD::EXTLOAD:
+ //include a conversion sequence for float loads to double
+ if (Result != notIn)
+ ExprMap[N.getValue(1)] = notIn; // Generate the token
+ else
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+
+ Tmp2 = MakeReg(MVT::f32);
+
+ if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
+ if (Node->getValueType(0) == MVT::f64) {
+ assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
+ "Bad EXTLOAD!");
+ BuildMI(BB, Alpha::LDS, 1, Tmp2).addConstantPoolIndex(CP->getIndex());
+ BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
+ return Result;
+ }
+ Select(Node->getOperand(0)); // chain
+ Tmp1 = SelectExpr(Node->getOperand(1));
+ BuildMI(BB, Alpha::LDS, 1, Tmp2).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
+ return Result;
+
+
+ //case ISD::UINT_TO_FP:
+
+ case ISD::SINT_TO_FP:
{
assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
- Tmp2 = MakeReg(DestType);
- //so these instructions are not supported on ev56
- Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
- BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
- Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
- BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+
+ //The hard way:
+ // Spill the integer to memory and reload it from there.
+ unsigned Size = MVT::getSizeInBits(MVT::i64)/8;
+ MachineFunction *F = BB->getParent();
+ int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
+
+ //STL LDS
+ //STQ LDT
+ Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL;
+ BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx);
+ Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
+ BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx);
+
+ //The easy way: doesn't work
+// //so these instructions are not supported on ev56
+// Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
+// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
+// Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
+// BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+
return Result;
}
}
@@ -400,9 +459,15 @@
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::ConstantPool:
+ Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+ AlphaLowering.restoreGP(BB);
+ BuildMI(BB, Alpha::LOAD, 1, Result).addConstantPoolIndex(Tmp1);
+ return Result;
+
case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
- BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
+ BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1);
return Result;
case ISD::EXTLOAD:
@@ -770,6 +835,7 @@
case ISD::XOR:
case ISD::SHL:
case ISD::SRL:
+ case ISD::SRA:
case ISD::MUL:
assert (DestType == MVT::i64 && "Only do arithmetic on i64s!");
if(N.getOperand(1).getOpcode() == ISD::Constant &&
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.8 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.9
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.8 Thu Jan 27 01:50:35 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Sat Jan 29 09:42:07 2005
@@ -326,9 +326,9 @@
//CVTQL F-P 17.030 Convert quadword to longword
def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
-//CVTST F-P 16.2AC Convert S_floating to T_floating
+def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating
//CVTTQ F-P 16.0AF Convert T_floating to quadword
-//CVTTS F-P 16.0AC Convert T_floating to S_floating
+def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating
//S_floating : IEEE Single
//T_floating : IEEE Double
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.4 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.5
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.4 Thu Jan 27 02:31:19 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Sat Jan 29 09:42:07 2005
@@ -50,7 +50,7 @@
unsigned SrcReg, int FrameIdx) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
+ BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx);
// assert(0 && "TODO");
}
@@ -60,7 +60,7 @@
unsigned DestReg, int FrameIdx) const{
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
- BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
+ BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx);
// assert(0 && "TODO");
}
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