[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Chris Lattner
lattner at cs.uiuc.edu
Fri Jan 21 16:32:07 PST 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.50 -> 1.51
---
Log message:
Fix problems with non-x86 targets.
---
Diffs of the changes: (+3 -3)
LegalizeDAG.cpp | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.50 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.51
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.50 Fri Jan 21 00:05:23 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 21 18:31:52 2005
@@ -902,7 +902,7 @@
// SAR. However, it is doubtful that any exist.
unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
MVT::getSizeInBits(ExtraVT);
- SDOperand ShiftCst = DAG.getConstant(BitsDiff, MVT::i8);
+ SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
Node->getOperand(0), ShiftCst);
Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
@@ -1302,7 +1302,6 @@
return true;
}
-
// ExpandLibCall - Expand a node into a call to a libcall. If the result value
// does not fit into a register, return the lo part and set the hi part to the
// by-reg argument. If it does fit into a single register, return the result
@@ -1518,7 +1517,8 @@
// The high part is obtained by SRA'ing all but one of the bits of the lo
// part.
unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
- Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, MVT::i8));
+ Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
+ TLI.getShiftAmountTy()));
break;
}
case ISD::ZERO_EXTEND:
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