[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86InstrInfo.cpp X86RegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.116 -> 1.117
X86InstrInfo.cpp updated: 1.35 -> 1.36
X86RegisterInfo.cpp updated: 1.97 -> 1.98
---
Log message:

Improve coverage of the X86 instruction set by adding 16-bit shift doubles.


---
Diffs of the changes:  (+45 -3)

Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.116 llvm/lib/Target/X86/X86InstrInfo.td:1.117
--- llvm/lib/Target/X86/X86InstrInfo.td:1.116	Wed Jan 19 01:11:01 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Wed Jan 19 01:31:24 2005
@@ -881,6 +881,12 @@
 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
                    "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
                    Imp<[CL],[]>, TB;
+def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
+                   "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   Imp<[CL],[]>, TB, OpSize;
+def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
+                   "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   Imp<[CL],[]>, TB, OpSize;
 
 let isCommutable = 1 in {  // These instructions commute to each other.
 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
@@ -889,6 +895,14 @@
 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
                      (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
                      "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
+def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
+                     (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
+                     "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
+                     TB, OpSize;
+def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
+                     (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
+                     "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
+                     TB, OpSize;
 }
 
 let isTwoAddress = 0 in {
@@ -904,6 +918,21 @@
   def SHRD32mri8 : Ii8<0xAC, MRMDestMem, 
                        (ops i32mem:$dst, R32:$src2, i8imm:$src3),
                        "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
+
+  def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
+                     "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                     Imp<[CL],[]>, TB, OpSize;
+  def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
+                    "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                    Imp<[CL],[]>, TB, OpSize;
+  def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
+                      (ops i16mem:$dst, R16:$src2, i8imm:$src3),
+                      "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
+                      TB, OpSize;
+  def SHRD16mri8 : Ii8<0xAC, MRMDestMem, 
+                       (ops i16mem:$dst, R16:$src2, i8imm:$src3),
+                       "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
+                       TB, OpSize;
 }
 
 


Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.35 llvm/lib/Target/X86/X86InstrInfo.cpp:1.36
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.35	Wed Jan 19 01:11:01 2005
+++ llvm/lib/Target/X86/X86InstrInfo.cpp	Wed Jan 19 01:31:24 2005
@@ -126,15 +126,24 @@
 ///
 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
   switch (MI->getOpcode()) {
+  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
+  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
   case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
+    unsigned Opc;
+    unsigned Size;
+    switch (MI->getOpcode()) {
+    default: assert(0 && "Unreachable!");
+    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
+    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
+    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
+    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
+    }
     unsigned Amt = MI->getOperand(3).getImmedValue();
     unsigned A = MI->getOperand(0).getReg();
     unsigned B = MI->getOperand(1).getReg();
     unsigned C = MI->getOperand(2).getReg();
-    unsigned Opc = X86::SHRD32rri8;
-    if (MI->getOpcode() == X86::SHRD32rri8) Opc = X86::SHLD32rri8;
-    return BuildMI(Opc, 3, A).addReg(B).addReg(C).addImm(32-Amt);
+    return BuildMI(Opc, 3, A).addReg(B).addReg(C).addImm(Size-Amt);
   }
   default:
     return TargetInstrInfo::commuteInstruction(MI);


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.97 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.98
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.97	Mon Jan 10 16:09:33 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Wed Jan 19 01:31:24 2005
@@ -225,6 +225,10 @@
     case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
     case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
     case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
+    case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
+    case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
+    case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
+    case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
     case X86::SETBr:     return MakeMInst( X86::SETBm,   FrameIndex, MI);
     case X86::SETAEr:    return MakeMInst( X86::SETAEm,  FrameIndex, MI);
     case X86::SETEr:     return MakeMInst( X86::SETEm,   FrameIndex, MI);