[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.40 -> 1.41
SelectionDAGISel.cpp updated: 1.26 -> 1.27
---
Log message:

Teach legalize to promote copy(from|to)reg, instead of making the isel pass
do it.  This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.



---
Diffs of the changes:  (+13 -26)

Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.40 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.41
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.40	Mon Jan 17 20:59:52 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Jan 18 11:54:55 2005
@@ -380,7 +380,11 @@
       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
         Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
       break;
-    case Expand: {
+    case Promote:
+      Tmp2 = PromoteOp(Node->getOperand(1));
+      Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
+      break;
+    case Expand:
       SDOperand Lo, Hi;
       ExpandOp(Node->getOperand(1), Lo, Hi);      
       unsigned Reg = cast<RegSDNode>(Node)->getReg();
@@ -390,10 +394,6 @@
              "Cannot expand multiple times yet (i64 -> i16)");
       break;
     }
-    case Promote:
-      assert(0 && "CopyToReg should not require promotion!");
-      abort();
-    }
     break;
 
   case ISD::RET:
@@ -917,6 +917,13 @@
     Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
     break;
+  case ISD::CopyFromReg:
+    Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
+                                Node->getOperand(0));
+    // Remember that we legalized the chain.
+    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
+    break;
+
   case ISD::SETCC:
     assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
            "SetCC type is not legal??");


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.26 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.27
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.26	Mon Jan 17 20:52:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Jan 18 11:54:55 2005
@@ -292,19 +292,7 @@
       FuncInfo.ValueMap.find(V);
     assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
 
-    MVT::ValueType RegVT = VT;
-    if (TLI.getTypeAction(VT) == 1)          // Must promote this value?
-      RegVT = TLI.getTypeToTransformTo(VT);
-
-    N = DAG.getCopyFromReg(VMI->second, RegVT, DAG.getEntryNode());
-
-    if (RegVT != VT)
-      if (MVT::isFloatingPoint(VT))
-        N = DAG.getNode(ISD::FP_ROUND, VT, N);
-      else
-        N = DAG.getNode(ISD::TRUNCATE, VT, N);
-
-    return N;
+    return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
   }
 
   const SDOperand &setValue(const Value *V, SDOperand NewN) {
@@ -843,14 +831,6 @@
   assert((Op.getOpcode() != ISD::CopyFromReg ||
           cast<RegSDNode>(Op)->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  MVT::ValueType VT = Op.getValueType();
-  if (TLI.getTypeAction(VT) == 1) {       // Must promote this value?
-    if (MVT::isFloatingPoint(VT))
-      Op = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-    else
-      Op = DAG.getNode(ISD::ZERO_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-  }
-
   return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
 }