[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp SelectionDAGPrinter.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.24 -> 1.25
SelectionDAG.cpp updated: 1.29 -> 1.30
SelectionDAGISel.cpp updated: 1.14 -> 1.15
SelectionDAGPrinter.cpp updated: 1.5 -> 1.6
---
Log message:

Add new ImplicitDef node, rename CopyRegSDNode class to RegSDNode.



---
Diffs of the changes:  (+14 -8)

Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.24 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.25
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.24	Thu Jan 13 11:59:25 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Jan 13 14:49:43 2005
@@ -244,6 +244,11 @@
     assert(getTypeAction(Node->getValueType(0)) == Legal &&
            "This must be legal!");
     break;
+  case ISD::ImplicitDef:
+    Tmp1 = LegalizeOp(Node->getOperand(0));
+    if (Tmp1 != Node->getOperand(0))
+      Result = DAG.getImplicitDef(cast<RegSDNode>(Node)->getReg());
+    break;
   case ISD::Constant:
     // We know we don't need to expand constants here, constants only have one
     // value and we check that it is fine above.
@@ -398,13 +403,12 @@
       // Legalize the incoming value (must be legal).
       Tmp2 = LegalizeOp(Node->getOperand(1));
       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
-        Result = DAG.getCopyToReg(Tmp1, Tmp2,
-                                  cast<CopyRegSDNode>(Node)->getReg());
+        Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
       break;
     case Expand: {
       SDOperand Lo, Hi;
       ExpandOp(Node->getOperand(1), Lo, Hi);      
-      unsigned Reg = cast<CopyRegSDNode>(Node)->getReg();
+      unsigned Reg = cast<RegSDNode>(Node)->getReg();
       Result = DAG.getCopyToReg(Tmp1, Lo, Reg);
       Result = DAG.getCopyToReg(Result, Hi, Reg+1);
       assert(isTypeLegal(Result.getValueType()) &&
@@ -748,7 +752,7 @@
   }
 
   case ISD::CopyFromReg: {
-    unsigned Reg = cast<CopyRegSDNode>(Node)->getReg();
+    unsigned Reg = cast<RegSDNode>(Node)->getReg();
     // Aggregate register values are always in consequtive pairs.
     Lo = DAG.getCopyFromReg(Reg, NVT);
     Hi = DAG.getCopyFromReg(Reg+1, NVT);


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.29 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.30
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.29	Thu Jan 13 11:59:10 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Jan 13 14:49:43 2005
@@ -880,6 +880,7 @@
   case ISD::ConstantPool:  return "ConstantPoolIndex";
   case ISD::CopyToReg:     return "CopyToReg";
   case ISD::CopyFromReg:   return "CopyFromReg";
+  case ISD::ImplicitDef:   return "ImplicitDef";
 
   case ISD::ADD:    return "add";
   case ISD::SUB:    return "sub";
@@ -1006,7 +1007,7 @@
     if (LBB)
       std::cerr << LBB->getName() << " ";
     std::cerr << (const void*)BBDN->getBasicBlock() << ">";
-  } else if (const CopyRegSDNode *C2V = dyn_cast<CopyRegSDNode>(this)) {
+  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) {
     std::cerr << "<reg #" << C2V->getReg() << ">";
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(this)) {


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.14 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.15
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.14	Thu Jan 13 13:53:14 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Jan 13 14:49:43 2005
@@ -772,8 +772,9 @@
 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
   SelectionDAG &DAG = SDL.DAG;
   SDOperand Op = SDL.getValue(V);
-  if (CopyRegSDNode *CR = dyn_cast<CopyRegSDNode>(Op))
-    assert(CR->getReg() != Reg && "Copy from a reg to the same reg!");
+  assert((Op.getOpcode() != ISD::CopyFromReg ||
+          cast<RegSDNode>(Op)->getReg() != Reg) &&
+         "Copy from a reg to the same reg!");
   return DAG.getCopyToReg(DAG.getRoot(), Op, Reg);
 }
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.5 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.6
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.5	Tue Jan 11 16:21:04 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Thu Jan 13 14:49:43 2005
@@ -85,7 +85,7 @@
     if (LBB)
       Op += LBB->getName();
     //Op += " " + (const void*)BBDN->getBasicBlock();
-  } else if (const CopyRegSDNode *C2V = dyn_cast<CopyRegSDNode>(Node)) {
+  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(Node)) {
     Op += " #" + utostr(C2V->getReg());
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(Node)) {