[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.td updated: 1.16 -> 1.17
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Log message:

Minor optimization to allocate R8 registers in a better order.


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Diffs of the changes:  (+7 -1)

Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.16 llvm/lib/Target/X86/X86RegisterInfo.td:1.17
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.16	Thu Dec  2 12:17:31 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Wed Jan  5 10:09:16 2005
@@ -61,7 +61,13 @@
 // top-level register classes.  The order specified in the register list is
 // implicitly defined to be the register allocation order.
 //
-def R8  : RegisterClass<i8,  8, [AL, AH, CL, CH, DL, DH, BL, BH]>;
+
+// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
+// dependences between upper and lower parts of the register.  BL and BH are
+// last because they are call clobbered. Both Athlon and P4 chips suffer this
+// issue.
+def R8  : RegisterClass<i8,  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
+
 def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {