[llvm-commits] CVS: reopt/lib/Inst/lib/BinInterface/BitMath.h README SparcDis.cpp SparcDis.h SparcV9.h
Brian Gaeke
gaeke at cs.uiuc.edu
Sun Dec 5 18:14:20 PST 2004
Changes in directory reopt/lib/Inst/lib/BinInterface:
BitMath.h added (r1.1)
README added (r1.1)
SparcDis.cpp added (r1.1)
SparcDis.h added (r1.1)
SparcV9.h added (r1.1)
---
Log message:
Streamline the interfaces here so that usage of BinInterface is minimized.
Move the pieces of BinInterface that this code uses here, and dump the rest.
---
Diffs of the changes: (+1470 -0)
Index: reopt/lib/Inst/lib/BinInterface/BitMath.h
diff -c /dev/null reopt/lib/Inst/lib/BinInterface/BitMath.h:1.1
*** /dev/null Sun Dec 5 20:14:19 2004
--- reopt/lib/Inst/lib/BinInterface/BitMath.h Sun Dec 5 20:14:06 2004
***************
*** 0 ****
--- 1,143 ----
+ //===-- BinInterface/BitMath.h -----------------------------------*- C++ -*--=//
+ //
+ // High Performance Bit Utility Functions
+ // Contains
+ // * Routines for rounding to specific powers of 2
+ // * Bitfield access macros
+ // * Sign extend macro
+ // * Extract bitmask of lowest bit set
+ // * Fast bit-set counting for sparse and dense bitfields
+ // * Fast modulo 3 test and remainder calculation
+ // * Fast parity calculation
+ // * Fast log2 (for 32-bit numbers ONLY!)
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef BININTERFACE_BITMATH_H
+ #define BININTERFACE_BITMATH_H
+
+ #include "llvm/Support/DataTypes.h"
+
+ namespace llvm {
+
+ //*********************************
+ // Misc functions
+ //*********************************
+ #define P2KM1(k) ((1 << (k))-1) // (2 ^ K) - 1
+ #define ROUNDUP_P2(x, k) ((x+P2KM1(k)) &~ P2KM1(k))
+ #define ROUNDUP32(x) ROUNDUP_P2(x,5) // round up to nearest mult of 32
+
+
+ //*********************************
+ // Bitfield manipulation Macros
+ //*********************************
+ #define FLD_UPPER(FLD_DEF) (1 ? FLD_DEF)
+ #define FLD_LOWER(FLD_DEF) (0 ? FLD_DEF)
+ #define MASKBELOW(V) ((((uint64_t) 1) << V) - 1) // 64-bit '1' constant here to avoid overflow warnings
+ #define MASKEQBELOW(V) ((1 << V) | MASKBELOW(V)) //masks off everything ABOVE
+ #define RD_FLD(x, FLD) (unsigned)(((x & MASKEQBELOW(FLD_UPPER(FLD))) >> FLD_LOWER(FLD)))
+ #define MK_FLD(FLD, val) ((val << FLD_LOWER(FLD)) & MASKEQBELOW(FLD_UPPER(FLD)))
+ #define MASK_FLD(FLD) (MASKEQBELOW(FLD_UPPER(FLD)) & ~MASKBELOW(FLD_LOWER(FLD)))
+ #define RM_FLD(FLD, val) (val & ~(MASK_FLD(FLD)))
+
+ //**********************************
+ // Portable sign extend macros
+ //**********************************
+ #define SIGN_EXTEND13(x) (x & 0x1000 ? -(-x & 0x1FFF): x)
+ #define SIGN_EXTEND(x, bits) (x & (1 << (bits-1)) ? -(-x & ((1 << bits)-1)):x)
+
+ #define IS_POWER_2(x) !(x & (x-1))
+ #define LOWEST_BIT(x) (x & ~(x & (x-1)))
+ #define UPPER_BITS(x) (x & (x-1))
+
+ // Good if expected number of bits set < 4
+ static int countbits_sparse(unsigned m) //VALIDATED
+ {
+ int c = 0;
+ while (m)
+ {
+ c++;
+ m = UPPER_BITS(m);
+ }
+ return c;
+ }
+
+ // base 2 sum of digits (hardwired for 32-bit)
+ static int countbits_dense(unsigned w) //VALIDATED
+ {
+ w = (0x55555555 & w) + (0x55555555 & (w >> 1));
+ w = (0x33333333 & w) + (0x33333333 & (w >> 2));
+ w = (w + (w>>4)) & 0x0f0f0f0f;
+ w = w + (w>>16);
+ w = w + (w>>8);
+ return w&0xFF;
+ }
+
+ static bool ismod3(unsigned w) //VALIDATED
+ {
+ w = (w >> 16) + (w&0xFFFF);
+ w = (w >> 8) + (w&0xFF);
+ w = (w >> 4) + (w&0xF);
+ w = (w >> 2) + (w&0x3);
+ return (0xB6DB6DB6 >> w) & 1;
+ }
+
+
+ static int mod3(unsigned w) //VALIDATED
+ {
+ w = (w >> 16) + (w&0xFFFF);
+ w = (w >> 8) + (w&0xFF);
+ w = (w >> 4) + (w&0xF);
+ w = (w >> 2) + (w&0x3);
+ //use lookuptable
+ return (0x24924924 >> (w<<1)) & 3;
+ }
+
+
+ static int parity(unsigned w) //VALIDATED
+ {
+ w ^= w >> 16;
+ w ^= w >> 8;
+ w ^= w >> 4;
+ w ^= w >> 2;
+ w ^= w >> 1;
+ return w & 1;
+ }
+
+ //
+ // Note: users of this function may depend on the fact
+ // that log2(0) will return 0. Since it is
+ // undefined I have chosen this value.
+ //
+ static int log2_bits32(unsigned w) //VALIDATED
+ {
+ int n = 0;
+
+ if (w >> 16)
+ {
+ w >>= 16;
+ n+=16;
+ }
+ if (w >> 8)
+ {
+ w >>= 8;
+ n+=8;
+ }
+ if (w >> 4)
+ {
+ w >>= 4;
+ n+=4;
+ }
+
+ w <<= 1;
+ return ((0xFFFFAA50 >> w) & 3)+n; // this is a LUT
+ }
+
+ static unsigned LOW10(unsigned value) { return value & 0x000003ff; }
+ static unsigned HIGH22(unsigned value) { return value >> 10; }
+ static unsigned HIGHWORD(uint64_t value) { return (unsigned) (value >> 32); }
+ static unsigned LOWWORD(uint64_t value) { return (unsigned) value; }
+
+ } // end namespace llvm
+
+ #endif // BININTERFACE_BITMATH_H
Index: reopt/lib/Inst/lib/BinInterface/README
diff -c /dev/null reopt/lib/Inst/lib/BinInterface/README:1.1
*** /dev/null Sun Dec 5 20:14:19 2004
--- reopt/lib/Inst/lib/BinInterface/README Sun Dec 5 20:14:07 2004
***************
*** 0 ****
--- 1,16 ----
+
+ This contains a few pieces of BinInterface, which could originally be used to
+ analyze SPARC machine instructions, construct pseudo-SSA form, and manipulate
+ traces. It also includes a SPARC disassembler. It was primarily written by
+ Cameron Buschardt.
+
+ The only remaining user of BinInterface is the
+ Inst/lib/SparcInstManip.{cpp,h} module; therefore, the pieces which are
+ still used (SPARC binary instruction generator & disassembler) have
+ been moved into this directory.
+
+ Portability notes: Supports SPARC binaries only. Should compile & link
+ fine on X86.
+
+ Last modified $Date: 2004/12/06 02:14:07 $
+
Index: reopt/lib/Inst/lib/BinInterface/SparcDis.cpp
diff -c /dev/null reopt/lib/Inst/lib/BinInterface/SparcDis.cpp:1.1
*** /dev/null Sun Dec 5 20:14:19 2004
--- reopt/lib/Inst/lib/BinInterface/SparcDis.cpp Sun Dec 5 20:14:07 2004
***************
*** 0 ****
--- 1,726 ----
+ //===-- BinInterface/SparcDis.cpp --------------------------------*- C++ -*--=//
+ //
+ // SPARC Instruction Disassembler
+ //
+ // Disassembler API
+ //
+ // * Initial implementation
+ // * Added support for MOVcc (somehow I missed it?!)
+ // * Added support for pseudo-disassembly
+ // ( In the print routine for bin-interface we want
+ // to be able to print the internal SSA form with
+ // labels instead of registers. And we wish to
+ // ommit RD from the view when we are not explicitly
+ // reading from it)
+ //
+ // Todo:
+ // * On the instructions that don't read from RD
+ // do not print the label field (we get l-1 when we print)
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "BitMath.h" // binary math routines
+ #include "Sparc9.h" // SPARC9 opcode definitions
+ #include <cstdio>
+ #include <cassert>
+
+ using namespace llvm;
+
+ void sparc_printop_rs1(unsigned instr, int labelrs1)
+ {
+ if (labelrs1)
+ printf("l%d", labelrs1);
+ else
+ printf("%s", reg_names[RD_FLD(instr, INSTR_RS1)]);
+ }
+
+ void sparc_printop_rs2(unsigned instr, int labelrs2)
+ {
+ if (labelrs2)
+ printf("l%d", labelrs2);
+ else
+ printf("%s", reg_names[RD_FLD(instr, INSTR_RS2)]);
+ }
+
+ void sparc_printop_rrd(unsigned instr, int labelrrd)
+ {
+ if (labelrrd)
+ printf("l%d", labelrrd);
+ else
+ printf("%s", reg_names[RD_FLD(instr, INSTR_RD)]);
+ }
+
+ void sparc_printbr(unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
+ {
+ // look at the OP2 field
+ if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP)
+ printf("ILLTRAP");
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
+ {
+ if (RD_FLD(instr, INSTR_RD) == 0)
+ printf("NOP");
+ else
+ {
+ printf("SETHI %%hi(%08X), ", RD_FLD(instr, INSTR_IMM22) << 10);
+ sparc_printop_rrd(instr, labelrd);
+ }
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC || RD_FLD(instr, INSTR_OP2)==OP2_FB)
+ {
+ printf("b%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)],
+ SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22));
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BPICC ||
+ RD_FLD(instr, INSTR_OP2)==OP2_FBP)
+ {
+ printf("b%s",icond_names[RD_FLD(instr, INSTR_COND_H)]);
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
+ {
+ //A, RCOND_H, D16HI, P, RS1, D16LO
+ printf("P%s%s%s ", rcond_names[RD_FLD(instr, INSTR_RCOND_H)],
+ RD_FLD(instr, INSTR_A) ? ",a" : "",
+ RD_FLD(instr, INSTR_P) ? ",pt" : ",pn");
+ sparc_printop_rs1(instr, labelrs1);
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_FB)
+ {
+ // cond, A, disp22
+ printf("%s%s %08X", fcond_names[RD_FLD(instr, INSTR_COND_H)],
+ RD_FLD(instr, INSTR_A) ? ",a" : "",
+ RD_FLD(instr, INSTR_DISP22));
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BPICC)
+ {
+ // TODO
+ printf("[BPICC -- currently not handled]");
+ }
+ else{
+ printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2));
+ assert(0);
+ }
+ }
+
+ void sparc_printalu(const char * basename , unsigned instr, bool labels,
+ int labelrs1, int labelrs2, int labelrd, int labelccf)
+ {
+ // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13}
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ printf("%s ", basename);
+ if (!labels)
+ printf("%s, ", reg_names[RD_FLD(instr, INSTR_RD)]);
+ sparc_printop_rs1(instr, labelrs1);
+ printf(" ,");
+ sparc_printop_rs2(instr, labelrs2);
+ }
+ else
+ {
+ printf("%s ", basename);
+ if (!labels)
+ printf("%s, ", reg_names[RD_FLD(instr, INSTR_RD)]);
+ sparc_printop_rs1(instr, labelrs1);
+ printf(" , %d", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ }
+
+ void sparc_printshf(const char * basename, unsigned instr, bool labels,
+ int labelrs1, int labelrs2, int labelrd, int labelccf)
+ {
+ //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 ->
+ // {X=0 -> SHCNT32 X=1->SHCNT64 }}
+
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ printf("%s%d ", basename, (RD_FLD(instr, INSTR_X)==0 ? 32 : 64));
+ if (!labels)
+ printf("%s, ", reg_names[RD_FLD(instr, INSTR_RD)]);
+
+ sparc_printop_rs1(instr, labelrs1);
+ printf(", ");
+ sparc_printop_rs2(instr, labelrs2);
+ }
+ else
+ {
+
+ printf("%s%d ", basename, (RD_FLD(instr, INSTR_X)==0 ? 32 : 64));
+ if (!labels)
+ printf("%s, ", reg_names[RD_FLD(instr, INSTR_RD)]);
+
+
+ sparc_printop_rs1(instr, labelrs1);
+
+ printf(", 0x%04X, ", (RD_FLD(instr, INSTR_X)==0
+ ? RD_FLD(instr, INSTR_SHCNT32)
+ : RD_FLD(instr, INSTR_SHCNT64)));
+ if (!labels)
+ printf("%s", reg_names[RD_FLD(instr, INSTR_RD)]);
+ }
+
+ }
+
+ // Op2 class instructions
+ void sparc_printfpu(unsigned instr, bool labels, int labelrs1, int labelrs2,
+ int labelrd, int labelccf)
+ {
+ switch(RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON)
+ {
+ case OPF_FADDn:
+ printf("FADDn");
+ return;
+ case OPF_FSUBn:
+ printf("FSUBn");
+ return;
+ case OPF_FMOVn:
+ printf("FMOVn");
+ return;
+ case OPF_FNEGn:
+ printf("FNEGn");
+ return;
+ case OPF_FABSn:
+ printf("FABSn");
+ return;
+ case OPF_FMULn:
+ printf("FMULn");
+ return;
+ case OPF_FDIVn:
+ printf("FDIVn");
+ return;
+ case OPF_FSQRTn:
+ printf("FSQRTn");
+ return;
+ }
+ switch (RD_FLD(instr, INSTR_OPF) &~OPF_MASK_TO)
+ {
+ case OPF_FxTOt:
+ printf("FxTOt");
+ return;
+ case OPF_FiTOt:
+ printf("FiTOt");
+ return;
+ }
+
+ switch(RD_FLD(instr, INSTR_OPF))
+ {
+ case OPF_FsTOx:
+ printf("OPF_FsTOx");
+ return;
+ case OPF_FsTOi:
+ printf("OPF_FsTOi");
+ return;
+ case OPF_FsTOd:
+ printf("OPF_FsTOd");
+ return;
+ case OPF_FsTOq:
+ printf("OPF_FsTOq");
+ return;
+ case OPF_FdTOx:
+ printf("OPF_FdTOx");
+ return;
+ case OPF_FdTOi:
+ printf("OPF_FdTOi");
+ return;
+ case OPF_FqTOx:
+ printf("OPF_FqTOx");
+ return;
+ case OPF_FdTOs:
+ printf("OPF_FdTOs");
+ return;
+ case OPF_FdTOq:
+ printf("OPF_FdTOq");
+ return;
+ case OPF_FqTOi:
+ printf("OPF_FqTOi");
+ return;
+ case OPF_FqTOs:
+ printf("OPF_FqTOs");
+ return;
+ case OPF_FqTOd:
+ printf("OPF_FqTOd");
+ return;
+ case OPF_FsMULd:
+ printf("OPF_FsMULd");
+ return;
+ case OPF_FdMULq:
+ printf("OPF_FdMULq");
+ return;
+ }
+
+ assert(0); // we don't know the FPU instruction yet
+ }
+
+ void sparc_print2(unsigned instr, bool labels, int labelrs1, int labelrs2,
+ int labelrd, int labelccf)
+ {
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+
+ case OP3_MOVcc:
+ {
+ printf("mov%s(%s) ", icond_names[RD_FLD(instr, INSTR_COND_L)],
+ cc_names[(RD_FLD(instr, INSTR_CC2) << 2) | (RD_FLD(instr, INSTR_MOV_CC1) << 1) | RD_FLD(instr, INSTR_MOV_CC0)]);
+
+ if (!labels)
+ printf("%s, ", reg_names[RD_FLD(instr, INSTR_RD)]);
+
+ if (RD_FLD(instr, INSTR_I)==0) // RS2
+ sparc_printop_rs2(instr, labelrs2);
+ else
+ printf("%d", SIGN_EXTEND(RD_FLD(instr, INSTR_SIMM11), 11));
+
+
+ return;
+ }
+
+ case OP3_ADD:
+ sparc_printalu("ADD", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDcc:
+ sparc_printalu("ADDcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDC:
+ sparc_printalu("ADDC", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDCcc:
+ sparc_printalu("ADDCcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_AND:
+ sparc_printalu("AND", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDcc:
+ sparc_printalu("ANDcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_OR:
+ sparc_printalu("OR", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORcc:
+ sparc_printalu("ORcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XOR:
+ sparc_printalu("XOR", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XORcc:
+ sparc_printalu("XORcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUB:
+ sparc_printalu("SUB", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBcc:
+ sparc_printalu("SUBcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDN:
+ sparc_printalu("ANDN", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDNcc:
+ sparc_printalu("ANDNcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORN:
+ sparc_printalu("ORN", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORNcc:
+ sparc_printalu("ORNcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XNOR:
+ sparc_printalu("XNOR", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XNORcc:
+ sparc_printalu("XNORcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBC:
+ sparc_printalu("SUBC", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBCcc:
+ sparc_printalu("SUBCcc", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_MULX:
+ sparc_printalu("MULX", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SDIVX:
+ sparc_printalu("SDIVX", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_UDIVX:
+ sparc_printalu("UDIVX", instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SLL:
+ sparc_printshf("SLL",instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_SRL:
+ sparc_printshf("SRL",instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_SRA:
+ sparc_printshf("SRA",instr, labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_DONERETRY:
+ {
+ if (RD_FLD(instr, INSTR_FCN)==FCN_DONE)
+ printf("DONE");
+ else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY)
+ printf("RETRY");
+ return;
+ }
+
+ case OP3_FCMP:
+ {
+ unsigned fop_n =RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON;
+ if (fop_n==OPF_FCMPn)
+ printf("FCMP");
+ else if (fop_n==OPF_FCMPEn)
+ printf("FCMPE");
+ return;
+ }
+
+ case OP3_FPU:
+ sparc_printfpu(instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+ printf("OP3_FLUSH");
+ return;
+ case OP3_FLUSHW: //OP=OP_2 I = 0
+ printf("OP3_FLUSHW");
+ return;
+ case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ printf("jmpl link:");
+ sparc_printop_rrd(instr, labelrd);
+ printf(", to: ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+");
+ sparc_printop_rs2(instr, labelrs2);
+ }
+ else
+ {
+ printf("jmpl link:");
+ sparc_printop_rrd(instr, labelrd);
+ printf(", to: ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+%d",SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ return;
+
+ case OP3_POPC:
+ printf("POPC ????");
+ return;
+
+ case OP3_RETURN:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ printf("return ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+");
+ sparc_printop_rs2(instr, labelrs2);
+ }
+ else
+ {
+ printf("return ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+%d",SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ return;
+
+ case OP3_SAVE:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ printf("save ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf(", ");
+ sparc_printop_rs2(instr, labelrs2);
+ printf(", ");
+ sparc_printop_rrd(instr, labelrd);
+ }
+ else
+ {
+ printf("save ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf(", %d, ", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ sparc_printop_rrd(instr, labelrd);
+ }
+ return;
+
+ case OP3_RESTORE:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ printf("restore ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf(", ");
+ sparc_printop_rs2(instr, labelrs2);
+ printf(", ");
+ sparc_printop_rrd(instr, labelrd);
+ }
+ else
+ {
+ printf("restore ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf(", %d, ", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ sparc_printop_rrd(instr, labelrd);
+ }
+ return;
+
+
+ }
+
+ printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3));
+ assert(0);
+ }
+
+ void sparc_printload(const char * basename, unsigned instr, bool labels,
+ int labelrs1, int labelrs2, int labelrd , int labelccf)
+ {
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ printf("%s ", basename);
+ if (!labels)
+ {
+ sparc_printop_rrd(instr, labelrd);
+ printf(", ");
+ }
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+");
+ sparc_printop_rs2(instr, labelrs2);
+ }
+ else
+ {
+ printf("%s ", basename);
+ if (!labels)
+ {
+ sparc_printop_rrd(instr, labelrd);
+ printf(", ");
+ }
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+%d", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ }
+
+ void sparc_printstore(const char * basename, unsigned instr, bool labels,
+ int labelrs1, int labelrs2, int labelrd , int labelccf)
+ {
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ printf("%s ", basename);
+ sparc_printop_rrd(instr, labelrd);
+ printf(", ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+");
+ sparc_printop_rs2(instr, labelrs2);
+
+ }
+ else
+ {
+ printf("%s ", basename);
+ sparc_printop_rrd(instr, labelrd);
+ printf(", ");
+ sparc_printop_rs1(instr, labelrs1);
+ printf("+%d", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ }
+
+ void sparc_print3(unsigned instr, bool labels, int labelrs1, int labelrs2,
+ int labelrd, int labelccf)
+ {
+ // OP3_LDF OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+ // OP3_LDDFA OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+ // OP3_LDQFA OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+ // OP3_LDSTUB OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+ // OP3_LDSTUBA OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
+
+
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+ //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+ case OP3_LDSTUB:
+ sparc_printload("LDSTUB", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STB:
+ sparc_printstore("STB", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STH:
+ sparc_printstore("STH", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STW:
+ sparc_printstore("STW", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STX:
+ sparc_printstore("STX", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSB:
+ sparc_printload("LDSB", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSH:
+ sparc_printload("LDSH", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSW:
+ sparc_printload("LDSW", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUB:
+ sparc_printload("LDUB", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUH:
+ sparc_printload("LDUH", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUW:
+ sparc_printload("LDUW", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDX:
+ sparc_printload("LDX", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_CASA:
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("CASA [r%d] %%%d, r%d, r%d",
+ RD_FLD(instr, INSTR_RS1),
+ RD_FLD(instr, INSTR_IMMASI),
+ RD_FLD(instr, INSTR_RS2),
+ RD_FLD(instr, INSTR_RD));
+
+ else
+ printf("CASA [l%d] %%%d, l%d, l%d",
+ labelrs1,
+ RD_FLD(instr, INSTR_IMMASI),
+ labelrs2,
+ labelrd);
+ }
+ else
+ {
+ if (!labels)
+ printf("CASA [r%d] , r%d, r%d",
+ RD_FLD(instr, INSTR_RS1),
+ RD_FLD(instr, INSTR_RS2),
+ RD_FLD(instr, INSTR_RD));
+ else
+ printf("CASA [l%d] , l%d, l%d", labelrs1, labelrs2, labelrd);
+ }
+
+ sparc_printalu("CASA", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+
+ return;
+
+ case OP3_CASXA:
+ sparc_printalu("CASXA", instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STFA:
+ sparc_printalu("STFA",instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STDFA:
+ sparc_printalu("STDFA",instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STQFA:
+ sparc_printalu("STQFA",instr,labels,
+ labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_PREFETCH:
+ printf("PREFETCH ??? ");
+ return;
+
+ case OP3_PREFETCHA:
+ printf("PREFETCHA ??? ");
+ return;
+ }
+
+ printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3));
+ assert(0);
+ }
+
+ void sparc_print_pseudo(unsigned instr, int labelrs1, int labelrs2, int labelrd, int labelccf)
+ {
+ if (RD_FLD(instr,INSTR_OP)==OP_CALL)
+ printf("CALL disp:+%08X", instr & 0x3FFFFFFF);
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ sparc_printbr(instr,true,labelrs1, labelrs2, labelrd, labelccf);
+ else if (RD_FLD(instr,INSTR_OP)==OP_2)
+ sparc_print2(instr,true,labelrs1, labelrs2, labelrd, labelccf);
+ else if (RD_FLD(instr,INSTR_OP)==OP_3)
+ sparc_print3(instr,true,labelrs1, labelrs2, labelrd, labelccf);
+ }
+
+ void sparc_print(unsigned instr)
+ {
+ if (RD_FLD(instr,INSTR_OP)==OP_CALL)
+ printf("CALL disp:+%08X", instr & 0x3FFFFFFF);
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ sparc_printbr(instr,false,0, 0, 0, 0);
+ else if (RD_FLD(instr,INSTR_OP)==OP_2)
+ sparc_print2(instr,false,0, 0, 0, 0);
+ else if (RD_FLD(instr,INSTR_OP)==OP_3)
+ sparc_print3(instr,false,0, 0, 0, 0 );
+ }
Index: reopt/lib/Inst/lib/BinInterface/SparcDis.h
diff -c /dev/null reopt/lib/Inst/lib/BinInterface/SparcDis.h:1.1
*** /dev/null Sun Dec 5 20:14:19 2004
--- reopt/lib/Inst/lib/BinInterface/SparcDis.h Sun Dec 5 20:14:08 2004
***************
*** 0 ****
--- 1,36 ----
+ //===-- BinInterface/SparcDis.h ----------------------------------*- C++ -*--=//
+ //
+ // Disassembler API Header
+ //
+ // * Initial implementation
+ // * Added support for MOVcc (somehow I missed it?!)
+ // * Added support for pseudo-disassembly
+ // ( In the print routine for bin-interface we want
+ // to be able to print the internal SSA form with
+ // labels instead of registers. And we wish to
+ // ommit RD from the view when we are not explicitly
+ // reading from it)
+ //
+ // Todo:
+ // * On the instructions that don't read from RD
+ // do not print the label field (we get l-1 when we print)
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef BININTERFACE_SPARCDIS_H
+ #define BININTERFACE_SPARCDIS_H
+
+ namespace llvm {
+
+ // Conventional Disassembly. Prints instruction (no newline)
+ void sparc_print(unsigned instr);
+
+ // Pseudo disasm
+ // uses the integers in labelrs1, labelrs2, labelrd, and labelccf as
+ // gen labels for the parameter sources
+ // instead of printing rxx for rs1, it will print l__labelrs1__
+ void sparc_print_pseudo(unsigned instr, int labelrs1, int labelrs2, int labelrd, int labelccf);
+
+ } // end namespace llvm
+
+ #endif // BININTERFACE_SPARCDIS_H
Index: reopt/lib/Inst/lib/BinInterface/SparcV9.h
diff -c /dev/null reopt/lib/Inst/lib/BinInterface/SparcV9.h:1.1
*** /dev/null Sun Dec 5 20:14:19 2004
--- reopt/lib/Inst/lib/BinInterface/SparcV9.h Sun Dec 5 20:14:08 2004
***************
*** 0 ****
--- 1,549 ----
+ //===-- BinInterface/SparcV9.h -----------------------------------*- C++ -*--=//
+ //
+ // Portable SPARC v9 Machine Code Definition Header
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef BININTERFACE_SPARCV9_H
+ #define BININTERFACE_SPARCV9_H
+
+ namespace llvm {
+
+ //*****************************************************************************
+ // Register Names
+ //*****************************************************************************
+ #define R_I7 31
+ #define R_I6 30
+ #define R_I5 29
+ #define R_I4 28
+ #define R_I3 27
+ #define R_I2 26
+ #define R_I1 25
+ #define R_I0 24
+
+ #define R_L7 23
+ #define R_L6 22
+ #define R_L5 21
+ #define R_L4 20
+ #define R_L3 19
+ #define R_L2 18
+ #define R_L1 17
+ #define R_L0 16
+
+ #define R_O7 15
+ #define R_O6 14
+ #define R_O5 13
+ #define R_O4 12
+ #define R_O3 11
+ #define R_O2 10
+ #define R_O1 9
+ #define R_O0 8
+
+ #define R_G7 7
+ #define R_G6 6
+ #define R_G5 5
+ #define R_G4 4
+ #define R_G3 3
+ #define R_G2 2
+ #define R_G1 1
+ #define R_G0 0
+
+ #define R_SP R_O6
+ #define R_BP R_I6 // frame pointer
+
+ #define BR_ANNUL 1
+ #define BR_NOT_ANNUL 0
+ #define BPR 3
+ #define Bicc 2
+ #define Bpcc 1
+ #define FBfcc 6
+ #define FBPfcc 5
+ #define NOT_TAKEN_BR 0
+ #define TAKEN_BR 1
+
+ extern const char * reg_names[];
+
+ //*****************************************************************************
+ // Instruction bitfield definitions
+ //*****************************************************************************
+ #define INSTR_OP 31:30
+ #define INSTR_A 29:29
+ #define INSTR_FCN 29:25
+ #define INSTR_DISP30 29:0
+ #define INSTR_COND_H 28:25
+ #define INSTR_RCOND_H 27:25
+ #define INSTR_CC1_H 26:26
+ #define INSTR_CC0_H 25:25
+ #define INSTR_OP2 24:22
+ #define INSTR_OP3 24:19
+ #define INSTR_CC1_L 21:21
+ #define INSTR_D16HI 21:20
+ #define INSTR_D16LO 13:0
+ #define INSTR_IMM22 21:0
+ #define INSTR_DISP22 21:0
+ #define INSTR_CC0_L 20:20
+ #define INSTR_P 19:19
+ #define INSTR_CC2 18:18
+ #define INSTR_MOV_CC0 11:11
+ #define INSTR_MOV_CC1 12:12
+ #define INSTR_DISP19 18:0
+ #define INSTR_IMPLDEP 18:0
+ #define INSTR_COND_L 17:14
+ #define INSTR_I 13:13
+ #define INSTR_OPFCC 13:11
+ #define INSTR_OPF 13:5
+ #define INSTR_X 12:12
+ #define INSTR_RCOND_L 12:10
+ #define INSTR_IMMASI 12:5
+ #define INSTR_SIMM13 12:0
+ #define INSTR_OPFLOW_B 10:5
+ #define INSTR_OPFLOW_S 9:5
+ #define INSTR_SIMM11 10:0
+ #define INSTR_SIMM10 9:0
+ #define INSTR_CMASK 6:4
+ #define INSTR_SWTRAP 6:0
+ #define INSTR_SHCNT64 5:0
+ #define INSTR_SHCNT32 4:0
+ #define INSTR_MMASK 3:0
+
+ #define INSTR_RS1 18:14
+ #define INSTR_RS2 4:0
+ #define INSTR_RD 29:25
+
+ #define INSTR_BRANCH_ANNUL 29:29
+ #define INSTR_BPR_COND 27:25
+ #define INSTR_INTBR_COND 28:25
+ #define INSTR_BPR 24:22
+ #define INSTR_INT_BR 24:22
+ #define BR_PREDICT 19:19
+
+ #define RD_D16(i) ((RD_FLD(i, INSTR_D16HI) << 14) | RD_FLD(i, INSTR_D16LO))
+
+
+ //*****************************************************************************
+ // Op-code classification
+ //*****************************************************************************
+ #define OP_CALL 0x00000001 /* 0b01 */
+ #define OP_BRANCH 0x00000000 /* 0b00 */
+ #define OP_2 0x00000002 /* 0b10 */
+ #define OP_3 0x00000003 /* 0b11 */
+
+ //*****************************************************************************
+ // Branch Class Instructions
+ //*****************************************************************************
+ #define OP2_ILLTRAP 0x00000000 /* 0b000 */ //OP=OP_BRANCH
+ #define OP2_NOP 0x00000004 /* 0b100 */ //BRANCH
+ #define OP2_SETHI 0x00000004 /* 0b100 */ //BRANCH - uhh? duplicate?
+ //DOH =p
+ #define OP2_BICC 0x00000002 /* 0b010 */
+ #define OP2_BPR 0x00000003 /* 0b011 */
+ #define OP2_FB 0x00000006 /* 0b110 */
+ #define OP2_FBP 0x00000005 /* 0b101 */
+ #define OP2_BPICC 0x00000001 /* 0b001 */
+
+ //*****************************************************************************
+ // Register Condition Codes
+ //*****************************************************************************
+ #define RCOND_RZ 0x00000001 /* 0b001 */
+ #define RCOND_RLEZ 0x00000002 /* 0b010 */
+ #define RCOND_RNZ 0x00000005 /* 0b101 */
+ #define RCOND_RGZ 0x00000006 /* 0b110 */
+ #define RCOND_RGEZ 0x00000007 /* 0b111 */
+
+ //*****************************************************************************
+ // FPU Branch Conditions
+ //*****************************************************************************
+ #define COND_FBN 0x00000000 /* 0b0000 */
+ #define COND_FBNE 0x00000001 /* 0b0001 */
+ #define COND_FBLG 0x00000002 /* 0b0010 */
+ #define COND_FBUL 0x00000003 /* 0b0011 */
+ #define COND_FBL 0x00000004 /* 0b0100 */
+ #define COND_FBUG 0x00000005 /* 0b0101 */
+ #define COND_FBG 0x00000006 /* 0b0110 */
+ #define COND_FBU 0x00000007 /* 0b0111 */
+ #define COND_FBA 0x00000008 /* 0b1000 */
+ #define COND_FBE 0x00000009 /* 0b1001 */
+ #define COND_FBUE 0x0000000A /* 0b1010 */
+ #define COND_FBGE 0x0000000B /* 0b1011 */
+ #define COND_FBUGE 0x0000000C /* 0b1100 */
+ #define COND_FBLE 0x0000000D /* 0b1101 */
+ #define COND_FBULE 0x0000000E /* 0b1110 */
+ #define COND_FBO 0x0000000F /* 0b1111 */
+
+ //*****************************************************************************
+ // Integer Branch Conditions
+ //*****************************************************************************
+ #define COND_BN 0x00000000 /* 0b0000 */
+ #define COND_BE 0x00000001 /* 0b0001 */
+ #define COND_BLE 0x00000002 /* 0b0010 */
+ #define COND_BL 0x00000003 /* 0b0011 */
+ #define COND_BLEU 0x00000004 /* 0b0100 */
+ #define COND_BCS 0x00000005 /* 0b0101 */
+ #define COND_BNEG 0x00000006 /* 0b0110 */
+ #define COND_BVS 0x00000007 /* 0b0111 */
+ #define COND_BA 0x00000008 /* 0b1000 */
+ #define COND_BNE 0x00000009 /* 0b1001 */
+ #define COND_BG 0x0000000A /* 0b1010 */
+ #define COND_BGE 0x0000000B /* 0b1011 */
+ #define COND_BGU 0x0000000C /* 0b1100 */
+ #define COND_BCC 0x0000000D /* 0b1101 */
+ #define COND_BPOS 0x0000000E /* 0b1110 */
+ #define COND_BVC 0x0000000F /* 0b1111 */
+
+
+ //*****************************************************************************
+ // Name Lookup tables
+ // index is Condition code
+ //*****************************************************************************
+
+ extern const char * fcond_names[];
+ extern const char * icond_names[];
+ extern const char * rcond_names[];
+
+ //*****************************************************************************
+ // Flag register encoding
+ //*****************************************************************************
+
+ #define FLAG_FCC0 0x00000000 /* 0b000 */
+ #define FLAG_FCC1 0x00000001 /* 0b001 */
+ #define FLAG_FCC2 0x00000002 /* 0b010 */
+ #define FLAG_FCC3 0x00000003 /* 0b011 */
+ #define FLAG_ICC 0x00000004 /* 0b100 */
+ #define FLAG_XCC 0x00000006 /* 0b110 */
+
+ extern const char * cc_names[];
+
+
+ //*****************************************************************************
+ // OP_2 class instructions
+ //
+ // present members:
+ // RD, OP3, RS1
+ // if I=0
+ // RS2
+ // else
+ // SIMM13
+ //*****************************************************************************
+
+ #define OP3_ADD 0x00000000 /* 0b000000 */
+ #define OP3_ADDC 0x00000008 /* 0b001000 */
+ #define OP3_AND 0x00000001 /* 0b000001 */
+ #define OP3_OR 0x00000002 /* 0b000010 */
+ #define OP3_XOR 0x00000003 /* 0b000011 */
+ #define OP3_SUB 0x00000004 /* 0b000100 */
+ #define OP3_ANDN 0x00000005 /* 0b000101 */
+ #define OP3_ORN 0x00000006 /* 0b000110 */
+ #define OP3_XNOR 0x00000007 /* 0b000111 */
+ #define OP3_SUBC 0x0000000C /* 0b001100 */
+ #define OP3_ADDcc 0x00000010 /* 0b010000 */
+ #define OP3_ADDCcc 0x00000018 /* 0b011000 */
+ #define OP3_ANDcc 0x00000011 /* 0b010001 */
+ #define OP3_ORcc 0x00000012 /* 0b010010 */
+ #define OP3_XORcc 0x00000013 /* 0b010011 */
+ #define OP3_SUBcc 0x00000014 /* 0b010100 */
+ #define OP3_ANDNcc 0x00000015 /* 0b010101 */
+ #define OP3_ORNcc 0x00000016 /* 0b010110 */
+ #define OP3_XNORcc 0x00000017 /* 0b010111 */
+ #define OP3_SUBCcc 0x0000001C /* 0b011100 */
+ #define OP3_MULX 0x00000009 /* 0b001001 */
+ #define OP3_SDIVX 0x0000002D /* 0b101101 */
+ #define OP3_UDIVX 0x0000000D /* 0b001101 */
+
+ //Op3 members
+ #define OP3_CASA 0x0000003C /* 0b111100 */
+ #define OP3_CASXA 0x0000003E /* 0b111110 */
+
+ //Instructions below generated with:
+ //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }}
+ #define OP3_SLL 0x00000025 /* 0b100101 */
+ #define OP3_SRL 0x00000026 /* 0b100110 */
+ #define OP3_SRA 0x00000027 /* 0b100111 */
+
+ // class OP_3
+ #define OP3_STFA 0x00000034 /* 0b110100 */
+ #define OP3_STDFA 0x00000037 /* 0b110111 */
+ #define OP3_STQFA 0x00000036 /* 0b110110 */
+
+ //Instructions below generated with:
+ //OP=OP_2: FCN
+ #define OP3_DONERETRY 0x0000003E /* 0b111110 */
+ #define FCN_DONE 0
+ #define FCN_RETRY 1
+
+ //These masks are valid for the instructions below
+ #define OPF_MASK_ONs 0x00000001 /* 0b0001 */ //these are valid for 'n' field
+ #define OPF_MASK_ONd 0x00000002 /* 0b0010 */
+ #define OPF_MASK_ONq 0x00000003 /* 0b0011 */
+ #define OPF_MASK_TOs 0x00000004 /* 0b0100 */ //these are valid for 't' field
+ #define OPF_MASK_TOd 0x00000008 /* 0b1000 */
+ #define OPF_MASK_TOq 0x0000000C /* 0b1100 */
+
+ #define OPF_MASK_ON 0x00000003 /* 0b0011 */
+ #define OPF_MASK_TO 0x0000000C /* 0b1100 */
+
+ //Instructions below generated with
+ //OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2
+ #define OP3_FCMP 0x00000035 /* 0b110101 */
+ #define OPF_FCMPn 0x00000050 /* 0b001010000 */
+ #define OPF_FCMPEn 0x00000054 /* 0b001010100 */
+
+ //Instructions below generated with
+ //OP=OP_2: RD, OP3 RS1, OPF, RS2
+ #define OP3_FPU 0x00000034 /* 0b110100 */
+ #define OPF_FADDn 0x00000040 /* 0b001000000 */
+ #define OPF_FSUBn 0x00000044 /* 0b001000100 */
+ #define OPF_FMOVn 0x00000000 /* 0b000000000 */
+ #define OPF_FNEGn 0x00000004 /* 0b000000100 */
+ #define OPF_FABSn 0x00000008 /* 0b000001000 */
+ #define OPF_FMULn 0x00000048 /* 0b001001000 */
+ #define OPF_FDIVn 0x0000004C /* 0b001001100 */
+ #define OPF_FSQRTn 0x00000028 /* 0b000101000 */
+ #define OPF_FsTOx 0x00000081 /* 0b010000001 */
+ #define OPF_FsTOi 0x000000D1 /* 0b011010001 */
+ #define OPF_FsTOd 0x000000C9 /* 0b011001001 */
+ #define OPF_FsTOq 0x000000CD /* 0b011001101 */
+ #define OPF_FdTOx 0x00000082 /* 0b010000010 */
+ #define OPF_FdTOi 0x000000D2 /* 0b011010010 */
+ #define OPF_FdTOs 0x000000C6 /* 0b011000110 */
+ #define OPF_FdTOq 0x000000CE /* 0b011001110 */
+ #define OPF_FqTOx 0x00000083 /* 0b010000011 */
+ #define OPF_FqTOi 0x000000D3 /* 0b011010011 */
+ #define OPF_FqTOs 0x000000C7 /* 0b011000111 */
+ #define OPF_FqTOd 0x000000CB /* 0b011001011 */
+ #define OPF_FxTOt 0x00000080 /* 0b010000000 */
+ #define OPF_FiTOt 0x000000C0 /* 0b011000000 */
+ #define OPF_FsMULd 0x00000069 /* 0b001101001 */
+ #define OPF_FdMULq 0x0000006E /* 0b001101110 */
+
+
+ #define OP3_FLUSH 0x0000003B /* 0b111011 */
+ //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+
+ #define OP3_FLUSHW 0x0000002B /* 0b101011 */
+ //OP=OP_2 I = 0
+
+ #define OP3_JMPL 0x00000038 /* 0b111000 */
+ //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+
+ #define OP3_LDFA 0x00000030 /* 0b110000 */
+ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+ #define OP3_LDDFA 0x00000033 /* 0b110011 */
+ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+ #define OP3_LDQFA 0x00000032 /* 0b110010 */
+ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+ #define OP3_LDSTUB 0x0000000D /* 0b001101 */
+ //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+
+ #define OP3_STB 0x00000005 /* 0b000101 */
+ #define OP3_STH 0x00000006 /* 0b000110 */
+ #define OP3_STW 0x00000004 /* 0b000100 */
+
+ #define OP3_STD 0x00000007
+ #define OP3_STX 0x0000000e /* 0b001110 */
+
+ #define OP3_LDSB 0x00000009 /* 0b001001 */
+ #define OP3_LDSH 0x0000000A /* 0b001010 */
+ #define OP3_LDSW 0x00000008 /* 0b001000 */
+ #define OP3_LDUB 0x00000001 /* 0b000001 */
+ #define OP3_LDUH 0x00000002 /* 0b000010 */
+ #define OP3_LDUW 0x00000000 /* 0b000000 */
+ #define OP3_LDX 0x0000000B /* 0b001011 */
+
+
+
+ #define OP3_LDSTUBA 0x0000001D /* 0b011101 */
+ //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
+
+ #define OP3_MEMBAR 0x00000028 /* 0b101000 */
+ //OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
+
+ //These two instructions are FUNKY as hell
+ #define OP3_FMOVcc 0x00000035 /* 0b110101 */
+ //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
+
+ #define OP3_MOVcc 0x0000002C /* 0b101100 */ //
+
+
+ #define OP3_POPC 0x0000002E /* 0b101110 */
+ #define OP3_PREFETCH 0x0000002D /* 0b101101 */
+ #define OP3_PREFETCHA 0x0000003D /* 0b111101 */
+ #define OP3_RETURN 0x00000039 /* 0b111001 */
+ #define OP3_SAVE 0x0000003C /* 0b111100 */
+ #define OP3_RESTORE 0x0000003D /* 0b111101 */
+
+ #define OP3_SAVDRESTD 0x00000031 /* 0b110001 */
+ #define FCN_SAVED 0
+ #define FCN_RESTORED 1
+
+ #define OP3_TRAP 0x0000003A /* 0b111010 */ //integer trap
+
+
+ //*****************************************************************************
+ // Macros for generating useful instructions
+ //*****************************************************************************
+
+ // Generic Load worm Reg+Offs
+ #define MK_LDX_ROFFS(dreg,regoffs ,stackoffs) \
+ (MK_FLD(INSTR_OP, OP_3) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_LDX) | \
+ MK_FLD(INSTR_RS1, regoffs) | \
+ MK_FLD(INSTR_I , 1 ) | \
+ MK_FLD(INSTR_SIMM13, stackoffs))
+
+
+ // Load a word from O6/SP + stackoffs into dreg
+ #define MK_LDX_STACK(dreg, stackoffs) \
+ (MK_FLD(INSTR_OP, OP_3) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_LDX) | \
+ MK_FLD(INSTR_RS1, R_SP) | \
+ MK_FLD(INSTR_I , 1 ) | \
+ MK_FLD(INSTR_SIMM13, stackoffs))
+
+
+ // Move a value between two registers
+ #define MK_MOV_R_R(dreg, sreg) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_MOVcc) | \
+ MK_FLD(INSTR_RS2, sreg) | \
+ MK_FLD(INSTR_I , 0 ) | \
+ MK_FLD(INSTR_COND_L, COND_BA) | \
+ MK_FLD(INSTR_CC2 , 1 ) | \
+ MK_FLD(INSTR_MOV_CC1 , 1 ) | \
+ MK_FLD(INSTR_MOV_CC0, 0 ))
+
+ // Store a word in sreg to O6/SP + stackoffs
+ #define MK_STX_STACK(sreg, stackoffs) \
+ (MK_FLD(INSTR_OP, OP_3) | \
+ MK_FLD(INSTR_RD, sreg) | \
+ MK_FLD(INSTR_OP3, OP3_STX) | \
+ MK_FLD(INSTR_RS1, R_SP) | \
+ MK_FLD(INSTR_I , 1 ) | \
+ MK_FLD(INSTR_SIMM13, stackoffs))
+
+ // Add a constant to a register
+ #define MK_ADD_R_I(dreg, sreg, imm) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_SIMM13, imm) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_OP3, OP3_ADD))
+
+ #define MK_INSTR_BRANCH_RS1(cond) \
+ (MK_FLD(INSTR_OP, OP_BRANCH) | \
+ MK_FLD(INSTR_BPR, BPR) | \
+ MK_FLD(INSTR_BPR_COND, cond))
+
+ #define MK_INSTR_BRANCH_NO_RS1(cond) \
+ (MK_FLD(INSTR_OP, OP_BRANCH) | \
+ MK_FLD(INSTR_INT_BR, Bicc) | \
+ MK_FLD(INSTR_INTBR_COND, cond))
+
+ // Add a register to a register
+
+ #define MK_ADD_R_R(dreg, sreg1, sreg2) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_ADD) | \
+ MK_FLD(INSTR_RS1, sreg1) | \
+ MK_FLD(INSTR_I, 0) | \
+ MK_FLD(INSTR_RS2, sreg2))
+
+ // Construct immediate-valued logical operation
+
+ #define MK_LOGIC_IMM(op3, dreg, sreg, imm) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_SIMM13, imm) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_OP3, op3))
+
+ // Construct reg-to-reg logical operation
+
+ #define MK_LOGIC(op3, dreg, sreg1, sreg2) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_RS1, sreg1) | \
+ MK_FLD(INSTR_RS2, sreg2) | \
+ MK_FLD(INSTR_I, 0) | \
+ MK_FLD(INSTR_OP3, op3))
+
+ // Construct sethi instruction
+
+ #define MK_SETHI(dreg, imm) \
+ (MK_FLD(INSTR_OP, OP_BRANCH) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP2, OP2_SETHI) | \
+ MK_FLD(INSTR_IMM22, imm))
+
+ // Construct S{LL,RL,RA}X shift instruction.
+
+ #define MK_SHIFTX(op3, dreg, sreg, shcnt) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, op3) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_X, 1) | \
+ MK_FLD(INSTR_SHCNT64, shcnt))
+
+ #define MK_STORE_IMM(srcreg, basereg, offset) \
+ (MK_FLD(INSTR_OP, OP_3) | \
+ MK_FLD(INSTR_RD, srcreg) | \
+ MK_FLD(INSTR_OP3, OP3_STX) | \
+ MK_FLD(INSTR_RS1, basereg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_SIMM13, offset))
+
+ #define MK_LOAD_IMM(destreg, basereg, offset) \
+ (MK_FLD(INSTR_OP, OP_3) | \
+ MK_FLD(INSTR_RD, destreg) | \
+ MK_FLD(INSTR_OP3, OP3_LDX) | \
+ MK_FLD(INSTR_RS1, basereg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_SIMM13, offset))
+
+ // Construct save instruction
+
+ #define MK_SAVE_IMM(dreg, sreg, imm) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_SAVE) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_SIMM13, imm))
+
+ #define MK_SAVE_REG(dreg, sreg1, sreg2) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_SAVE) | \
+ MK_FLD(INSTR_RS1, sreg1) | \
+ MK_FLD(INSTR_I, 0) | \
+ MK_FLD(INSTR_RS2, sreg2))
+
+ #define MK_RESTORE_IMM(dreg, sreg, imm) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_RESTORE) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_SIMM13, imm))
+
+ #define MK_JMPL_INDIRECT(dreg, sreg, imm) \
+ (MK_FLD(INSTR_OP, OP_2) | \
+ MK_FLD(INSTR_RD, dreg) | \
+ MK_FLD(INSTR_OP3, OP3_JMPL) | \
+ MK_FLD(INSTR_RS1, sreg) | \
+ MK_FLD(INSTR_I, 1) | \
+ MK_FLD(INSTR_SIMM13, imm))
+
+ } // end namespace llvm
+
+ #endif // BININTERFACE_SPARCV9_H
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