[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelSimple.cpp updated: 1.110 -> 1.111
---
Log message:

Add the same optimization that we do loading from fixed alloca slots to
storing to fixed alloca slots.


---
Diffs of the changes:  (+12 -0)

Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.110 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.111
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.110	Tue Nov 23 00:05:44 2004
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Wed Nov 24 15:53:14 2004
@@ -2989,6 +2989,8 @@
   if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
   if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
 
+  // If this is a fixed size alloca, emit a load directly from the stack slot
+  // corresponding to it.
   if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
     unsigned FI = getFixedSizedAllocaFI(AI);
     if (Class == cLong) {
@@ -3071,6 +3073,16 @@
   unsigned IdxOpcode = IdxOpcodes[Class];
   unsigned ValReg    = getReg(I.getOperand(0));
 
+  // If this is a fixed size alloca, emit a store directly to the stack slot
+  // corresponding to it.
+  if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
+    unsigned FI = getFixedSizedAllocaFI(AI);
+    addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg), FI);
+    if (Class == cLong)
+      addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
+    return;
+  }
+  
   // If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
   // use the index from the FoldedGEP struct and use reg+reg addressing.
   if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {