[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9CodeEmitter.cpp updated: 1.75 -> 1.76
---
Log message:

Implement a disgusting hack to work around broken machine code emission of
the RDCCR instruction.  This fixes a bunch of programs with the JIT.


---
Diffs of the changes:  (+12 -1)

Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.75 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.76
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.75	Mon Nov 22 14:25:10 2004
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp	Mon Nov 22 15:25:10 2004
@@ -292,7 +292,18 @@
   currBB = MBB.getBasicBlock();
   BBLocations[currBB] = MCE.getCurrentPCValue();
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
-    emitWord(getBinaryCodeForInstr(*I));
+    if (I->getOpcode() != V9::RDCCR) {
+      emitWord(getBinaryCodeForInstr(*I));
+    } else {
+      // FIXME: The tblgen produced code emitter cannot deal with the fact that
+      // machine operand #0 of the RDCCR instruction should be ignored.  This is
+      // really a bug in the representation of the RDCCR instruction (which has
+      // no need to explicitly represent the CCR dest), but we hack around it
+      // here.
+      unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
+      RegNo &= (1<<5)-1;
+      emitWord((RegNo << 25) | 2168487936U);
+    }
 }