[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp README.txt

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelSimple.cpp updated: 1.101 -> 1.102
README.txt updated: 1.20 -> 1.21
---
Log message:

Put int the getReg cast optimization from x86 so that we generate fewer
move instructions for the register allocator to coalesce.


---
Diffs of the changes:  (+10 -0)

Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.101 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.102
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.101	Sun Nov  7 14:23:42 2004
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Sun Nov  7 20:25:40 2004
@@ -502,6 +502,10 @@
     unsigned Reg = makeAnotherReg(V->getType());
     copyConstantToRegister(MBB, IPt, C, Reg);
     return Reg;
+  } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
+    // Do not emit noop casts at all, unless it's a double -> float cast.
+    if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
+      return getReg(CI->getOperand(0), MBB, IPt);
   } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
     unsigned Reg = makeAnotherReg(V->getType());
     unsigned FI = getFixedSizedAllocaFI(AI);
@@ -3129,6 +3133,10 @@
   unsigned SrcClass = getClassB(Op->getType());
   unsigned DestClass = getClassB(CI.getType());
 
+  // Noop casts are not emitted: getReg will return the source operand as the
+  // register to use for any uses of the noop cast.
+  if (DestClass == SrcClass) return;
+
   // If this is a cast from a 32-bit integer to a Long type, and the only uses
   // of the cast are GEP instructions, then the cast does not need to be
   // generated explicitly, it will be folded into the GEP.


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.20 llvm/lib/Target/PowerPC/README.txt:1.21
--- llvm/lib/Target/PowerPC/README.txt:1.20	Mon Oct 25 23:10:53 2004
+++ llvm/lib/Target/PowerPC/README.txt	Sun Nov  7 20:25:40 2004
@@ -1,4 +1,6 @@
 TODO:
+* poor switch statement codegen
+* load/store to alloca'd array or struct.
 * implement not-R0 register GPR class
 * implement scheduling info
 * implement do-loop pass