[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp PPC64RegisterInfo.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.cpp updated: 1.6 -> 1.7
PPC64RegisterInfo.cpp updated: 1.6 -> 1.7
---
Log message:

Eliminate usage of MRegisterInfo::getRegClass(physreg)


---
Diffs of the changes:  (+18 -9)

Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.6 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.7
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.6	Mon Sep 27 00:07:25 2004
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Tue Oct 26 00:40:45 2004
@@ -48,6 +48,13 @@
   ImmToIdxMap[PPC::ADDI] = PPC::ADD;
 }
 
+static const TargetRegisterClass *getClass(unsigned SrcReg) {
+  if (PPC32::FPRCRegisterClass->contains(SrcReg))
+  	return PPC32::FPRCRegisterClass;
+  assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
+  return PPC32::GPRCRegisterClass;
+}
+
 static unsigned getIdx(const TargetRegisterClass *RC) {
   if (RC == PPC32::GPRCRegisterClass) {
     switch (RC->getSize()) {
@@ -71,12 +78,10 @@
 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD 
   };
-
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
@@ -94,8 +99,7 @@
   static const unsigned Opcode[] = { 
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD 
   };
-  const TargetRegisterClass *RC = getRegClass(DestReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);


Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.6 llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.7
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.6	Mon Sep 27 00:08:17 2004
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp	Tue Oct 26 00:40:45 2004
@@ -48,6 +48,13 @@
   ImmToIdxMap[PPC::ADDI] = PPC::ADD;
 }
 
+static const TargetRegisterClass *getClass(unsigned SrcReg) {
+  if (PPC64::FPRCRegisterClass->contains(SrcReg))
+  	return PPC64::FPRCRegisterClass;
+  assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
+  return PPC64::GPRCRegisterClass;
+}
+
 static unsigned getIdx(const TargetRegisterClass *RC) {
   if (RC == PPC64::GPRCRegisterClass) {
     switch (RC->getSize()) {
@@ -75,8 +82,7 @@
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
   };
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
@@ -94,8 +100,7 @@
   static const unsigned Opcode[] = { 
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD 
   };
-  const TargetRegisterClass *RC = getRegClass(DestReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);