[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td

[Misha Brukman]

Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrInfo.td updated: 1.39 -> 1.40
---
Log message:

Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.


---
Diffs of the changes:  (+7 -4)

Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.39 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.40
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.39	Sat Oct 23 00:38:55 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Sat Oct 23 01:05:49 2004
@@ -324,10 +324,13 @@
 
 // XFX-Form instructions.  Instructions that deal with SPRs
 //
-def MFCTR : XFXForm_1_ext<31, 339, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
-def MFLR  : XFXForm_1_ext<31, 339, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
-def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
-def MTLR  : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
+// Note that although LR should be listed as `8' and CTR as `9' in the SPR
+// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
+// which means the SPR value needs to be multiplied by a factor of 32.
+def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
+def MFLR  : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
+def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
+def MTLR  : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
 
 
 // XS-Form instructions.  Just 'sradi'