[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelSimple.cpp updated: 1.96 -> 1.97
---
Log message:

Kill casts from integer types to unsigned byte, when the cast was only used
as the shift amount operand to a shift instruction.  This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }


---
Diffs of the changes:  (+13 -0)

Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.96 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.97
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.96	Fri Oct 22 16:02:08 2004
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Fri Oct 22 19:50:23 2004
@@ -3014,6 +3014,19 @@
   unsigned DestReg = getReg(CI);
   MachineBasicBlock::iterator MI = BB->end();
 
+  // If this is a cast from an integer type to a ubyte, with one use where the
+  // use is the shift amount argument of a shift instruction, just emit a move
+  // instead (since the shift instruction will only look at the low 5 bits
+  // regardless of how it is sign extended)
+  if (CI.getType() == Type::UByteTy && SrcClass <= cInt && CI.hasOneUse()) {
+    ShiftInst *SI = dyn_cast<ShiftInst>(*(CI.use_begin()));
+    if (SI && (SI->getOperand(1) == &CI)) {
+      unsigned SrcReg = getReg(Op, BB, MI);
+      BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+      return; 
+    }
+  }
+
   // If this is a cast from an byte, short, or int to an integer type of equal
   // or lesser width, and all uses of the cast are store instructions then dont
   // emit them, as the store instruction will implicitly not store the zero or