[llvm-commits] CVS: llvm/lib/Target/PowerPC/Makefile PPC32ISelSimple.cpp

[Reid Spencer]

Changes in directory llvm/lib/Target/PowerPC:

Makefile updated: 1.13 -> 1.14
PPC32ISelSimple.cpp updated: 1.95 -> 1.96
---
Log message:

Adjust to changes in Makefile.rules

---
Diffs of the changes:  (+5 -37)

Index: llvm/lib/Target/PowerPC/Makefile
diff -u llvm/lib/Target/PowerPC/Makefile:1.13 llvm/lib/Target/PowerPC/Makefile:1.14
--- llvm/lib/Target/PowerPC/Makefile:1.13	Thu Oct 14 01:04:56 2004
+++ llvm/lib/Target/PowerPC/Makefile	Fri Oct 22 16:02:08 2004
@@ -8,45 +8,13 @@
 ##===----------------------------------------------------------------------===##
 LEVEL = ../../..
 LIBRARYNAME = powerpc
-include $(LEVEL)/Makefile.common
-
 TARGET = PowerPC
 
+
 # Make sure that tblgen is run, first thing.
-$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
-                 PowerPCGenAsmWriter.inc  PPC32GenCodeEmitter.inc \
+BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
+                PowerPCGenAsmWriter.inc  PPC32GenCodeEmitter.inc \
  PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
  PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
 
-TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
-
-%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
-	@echo "Building $(TARGET) register names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
-	@echo "Building `basename $<` register information header with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
-	@echo "Building `basename $<` register information implementation with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
-	@echo "Building $(TARGET) instruction names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
-	@echo "Building `basename $<` instruction information with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
-	@echo "Building `basename $<` code emitter with tblgen"
-	$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
-
-$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
-	@echo "Building $(TARGET).td assembly writer with tblgen"
-	$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
-
-clean::
-	$(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common


Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.95 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.96
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.95	Wed Oct 20 16:55:41 2004
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Fri Oct 22 16:02:08 2004
@@ -2144,7 +2144,7 @@
     if (CI_1 && OrI && OrI->getOpcode() == Instruction::Or) {
       Value *Op0 = OrI->getOperand(0);
       Value *Op1 = OrI->getOperand(1);
-      BinaryOperator *AndI_2;
+      BinaryOperator *AndI_2 = 0;
       // Whichever operand our initial And instruction is to the Or instruction,
       // Look at the other operand to determine if it is also an And instruction
       if (AndI == Op0) {