[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp PowerPCInstrInfo.td
Nate Begeman
natebegeman at mac.com
Sat Oct 16 13:44:07 PDT 2004
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelSimple.cpp updated: 1.92 -> 1.93
PowerPCInstrInfo.td updated: 1.37 -> 1.38
---
Log message:
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
---
Diffs of the changes: (+12 -12)
Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.92 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.93
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.92 Sat Oct 16 13:13:47 2004
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp Sat Oct 16 15:43:29 2004
@@ -2550,25 +2550,23 @@
// Longs, as usual, are handled specially...
if (Class == cLong) {
// If we have a constant shift, we can generate much more efficient code
- // than otherwise...
- //
+ // than for a variable shift by using the rlwimi instruction.
if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
unsigned Amount = CUI->getValue();
if (Amount < 32) {
+ unsigned TempReg = makeAnotherReg(ResultTy);
if (isLeftShift) {
- // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
- BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg)
.addImm(Amount).addImm(0).addImm(31-Amount);
- BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
- .addImm(Amount).addImm(32-Amount).addImm(31);
+ BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg).addReg(TempReg)
+ .addReg(SrcReg+1).addImm(Amount).addImm(32-Amount).addImm(31);
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
.addImm(Amount).addImm(0).addImm(31-Amount);
} else {
- // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
- BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg+1)
.addImm(32-Amount).addImm(Amount).addImm(31);
- BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
- .addImm(32-Amount).addImm(0).addImm(Amount-1);
+ BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
+ .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31);
}
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.37 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.38
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.37 Thu Oct 7 17:30:03 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Sat Oct 16 15:43:38 2004
@@ -412,9 +412,11 @@
// M-Form instructions. rotate and mask instructions.
//
+let isTwoAddress = 1 in {
def RLWIMI : MForm_2<20, 0, 0, 0,
- (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
- "rlwimi $rA, $rS, $SH, $MB, $ME">;
+ (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
+ u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
+}
def RLWINM : MForm_2<21, 0, 0, 0,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm $rA, $rS, $SH, $MB, $ME">;
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