[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32InstrInfo.cpp updated: 1.1 -> 1.2
---
Log message:

Add ori reg, reg, 0 as a move instruction.  This can be generated from
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr


---
Diffs of the changes:  (+11 -0)

Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.1 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.1	Mon Aug 16 23:55:41 2004
+++ llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp	Thu Oct  7 17:26:12 2004
@@ -46,6 +46,17 @@
       destReg = MI.getOperand(0).getReg();
       return true;
     }
+  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
+    assert(MI.getNumOperands() == 3 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(1).isRegister() &&
+           MI.getOperand(2).isImmediate() &&
+           "invalid PPC ORI instruction!");
+    if (MI.getOperand(2).getImmedValue()==0) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
   } else if (oc == PPC::FMR) {              // fmr r1, r2
     assert(MI.getNumOperands() == 2 &&
            MI.getOperand(0).isRegister() &&