[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelSimple.cpp

Chris Lattner lattner at cs.uiuc.edu
Tue Oct 5 21:02:50 PDT 2004



Changes in directory llvm/lib/Target/X86:

X86ISelSimple.cpp updated: 1.280 -> 1.281
---
Log message:

Codegen signed divides by 2 and -2 more efficiently.  In particular
instead of:

s:   ;; X / 2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        ret

t:   ;; X / -2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        negl %eax
        ret

Emit:

s:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        ret

t:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        negl %eax
        ret




---
Diffs of the changes:  (+22 -0)

Index: llvm/lib/Target/X86/X86ISelSimple.cpp
diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.280 llvm/lib/Target/X86/X86ISelSimple.cpp:1.281
--- llvm/lib/Target/X86/X86ISelSimple.cpp:1.280	Tue Sep 21 13:21:21 2004
+++ llvm/lib/Target/X86/X86ISelSimple.cpp	Tue Oct  5 23:02:39 2004
@@ -2695,6 +2695,28 @@
         return;
       }
 
+      if (V == 2 || V == -2) {      // X /s 2
+        static const unsigned CMPOpcode[] = {
+          X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
+        };
+        static const unsigned SBBOpcode[] = {
+          X86::SBB8ri, X86::SBB16ri, X86::SBB32ri
+        };
+        unsigned Op0Reg = getReg(Op0, BB, IP);
+        unsigned SignBit = 1 << (CI->getType()->getPrimitiveSize()*8-1);
+        BuildMI(*BB, IP, CMPOpcode[Class], 2).addReg(Op0Reg).addImm(SignBit);
+
+        unsigned TmpReg = makeAnotherReg(Op0->getType());
+        BuildMI(*BB, IP, SBBOpcode[Class], 2, TmpReg).addReg(Op0Reg).addImm(-1);
+
+        unsigned TmpReg2 = V == 2 ? ResultReg : makeAnotherReg(Op0->getType());
+        BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg2).addReg(TmpReg).addImm(1);
+        if (V == -2) {
+          BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(TmpReg2);
+        }
+        return;
+      }
+
       bool isNeg = false;
       if (V < 0) {         // Not a positive power of 2?
         V = -V;






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