[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td

[Misha Brukman]

Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.td updated: 1.13 -> 1.14
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Log message:

Fit long lines into 80 cols via creative space elimination


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Diffs of the changes:  (+4 -4)

Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.13 llvm/lib/Target/X86/X86RegisterInfo.td:1.14
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.13	Mon Sep 13 23:16:20 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Tue Sep 14 20:40:18 2004
@@ -36,10 +36,10 @@
   def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
   
   // 8-bit registers
-  def AL : RegisterGroup<"AL", [AX, EAX]>; def CL : RegisterGroup<"CL", [CX, ECX]>;
-  def DL : RegisterGroup<"DL", [DX, EDX]>; def BL : RegisterGroup<"BL", [BX, EBX]>;
-  def AH : RegisterGroup<"AH", [AX, EAX]>; def CH : RegisterGroup<"CH", [CX, ECX]>;
-  def DH : RegisterGroup<"DH", [DX, EDX]>; def BH : RegisterGroup<"BH", [BX, EBX]>;
+  def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
+  def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
+  def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
+  def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
   
   // Pseudo Floating Point registers
   def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;