[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td PowerPCInstrInfo.td
Nate Begeman
natebegeman at mac.com
Mon Aug 30 19:28:19 PDT 2004
Changes in directory llvm/lib/Target/PowerPC:
PowerPCInstrFormats.td updated: 1.17 -> 1.18
PowerPCInstrInfo.td updated: 1.31 -> 1.32
---
Log message:
convert M and MD form instructions to generated asm writer
---
Diffs of the changes: (+41 -20)
Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.17 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.18
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.17 Sun Aug 29 21:28:06 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td Mon Aug 30 21:28:08 2004
@@ -339,8 +339,8 @@
let L = ppc64;
}
-class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
- : I<name, opcode, ppc64, vmx> {
+class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
field bits<3> BF;
field bits<5> FRA;
field bits<5> FRB;
@@ -358,6 +358,8 @@
let Inst{16-20} = FRB;
let Inst{21-30} = xo;
let Inst{31} = 0;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
@@ -573,8 +575,8 @@
}
// 1.7.13 M-Form
-class MForm_1<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
- : I<name, opcode, ppc64, vmx> {
+class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
let ArgCount = 5;
field bits<5> RS;
field bits<5> RA;
@@ -594,16 +596,19 @@
let Inst{21-25} = MB;
let Inst{26-30} = ME;
let Inst{31} = rc;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
-class MForm_2<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
- : MForm_1<name, opcode, rc, ppc64, vmx> {
+class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr>
+ : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> {
let Arg2Type = Imm5.Value;
}
// 1.7.14 MD-Form
-class MDForm_1<string name, bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx>
- : I<name, opcode, ppc64, vmx> {
+class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
let ArgCount = 4;
field bits<5> RS;
field bits<5> RA;
@@ -623,6 +628,8 @@
let Inst{27-29} = xo;
let Inst{30} = SH{0};
let Inst{31} = rc;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.31 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.32
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.31 Sun Aug 29 21:28:06 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Mon Aug 30 21:28:08 2004
@@ -96,20 +96,12 @@
def STD : DSForm_2<"std", 62, 0, 1, 0>;
def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
-def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
-def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
-def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
-def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
-def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
-def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
-
def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
-def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
// D-Form instructions. Most instructions that perform an operation on a
// register and an immediate are of this type.
@@ -208,10 +200,12 @@
"extsh $rA, $rS">;
def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
"extsw $rA, $rS">;
-def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
- "lfsx $dst, $base, $index">;
-def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
- "lfdx $dst, $base, $index">;
+def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+ "fcmpu $crD, $fA, $fB">;
+def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+ "lfsx $dst, $base, $index">;
+def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+ "lfdx $dst, $base, $index">;
def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
"fcfid $frD, $frB">;
def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
@@ -322,3 +316,23 @@
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
"fsubs $FRT, $FRA, $FRB">;
+// M-Form instructions. rotate and mask instructions.
+//
+def RLWIMI : MForm_2<20, 0, 0, 0,
+ (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
+ "rlwimi $rA, $rS, $SH, $MB, $ME">;
+def RLWINM : MForm_2<21, 0, 0, 0,
+ (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
+ "rlwinm $rA, $rS, $SH, $MB, $ME">;
+
+
+// MD-Form instructions. 64 bit rotate instructions.
+//
+def RLDICL : MDForm_1<30, 0, 0, 1, 0,
+ (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
+ "rldicl $rA, $rS, $SH, $MB">;
+def RLDICR : MDForm_1<30, 1, 0, 1, 0,
+ (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
+ "rldicr $rA, $rS, $SH, $ME">;
+
+
More information about the llvm-commits
mailing list