[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp PowerPCInstrFormats.td PowerPCInstrInfo.td
Nate Begeman
natebegeman at mac.com
Sun Aug 29 19:28:16 PDT 2004
Changes in directory llvm/lib/Target/PowerPC:
PPC32AsmPrinter.cpp updated: 1.55 -> 1.56
PowerPCInstrFormats.td updated: 1.16 -> 1.17
PowerPCInstrInfo.td updated: 1.30 -> 1.31
---
Log message:
Move yet more instructions over to being printed by the generated asm writer
---
Diffs of the changes: (+183 -135)
Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.55 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.56
--- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.55 Sat Aug 21 14:11:03 2004
+++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Sun Aug 29 21:28:06 2004
@@ -92,6 +92,12 @@
assert(value <= 31 && "Invalid u5imm argument!");
O << (unsigned int)value;
}
+ void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo,
+ MVT::ValueType VT) {
+ unsigned char value = MI->getOperand(OpNo).getImmedValue();
+ assert(value <= 63 && "Invalid u6imm argument!");
+ O << (unsigned int)value;
+ }
void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.16 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.17
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.16 Sun Aug 29 17:45:13 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td Sun Aug 29 21:28:06 2004
@@ -427,8 +427,8 @@
}
// 1.7.8 XFX-Form
-class XFXForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
- : I<name, opcode, ppc64, vmx> {
+class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
field bits<5> ST;
field bits<10> SPR;
@@ -443,21 +443,26 @@
let Inst{11-20} = SPR;
let Inst{21-30} = xo;
let Inst{31} = 0;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
-class XFXForm_1_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
- bit ppc64, bit vmx> : XFXForm_1<name,opcode,xo,ppc64,vmx> {
+class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
+ bit vmx, dag OL, string asmstr>
+ : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
let ArgCount = 1;
let Arg0Type = Gpr.Value;
let Arg1Type = 0;
let SPR = spr;
}
-class XFXForm_7<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
- : XFXForm_1<name, opcode, xo, ppc64, vmx>;
-
-class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
- bit ppc64, bit vmx> : XFXForm_7<name,opcode,xo,ppc64,vmx> {
+class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
+ dag OL, string asmstr>
+ : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
+
+class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
+ bit ppc64, bit vmx, dag OL, string asmstr>
+ : XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
let ArgCount = 1;
let Arg0Type = Gpr.Value;
let Arg1Type = 0;
@@ -465,8 +470,8 @@
}
// 1.7.10 XS-Form
-class XSForm_1<string name, bits<6> opcode, bits<9> xo, bit rc,
- bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
+class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
field bits<5> RS;
field bits<5> A;
field bits<6> SH;
@@ -484,11 +489,13 @@
let Inst{21-29} = xo;
let Inst{30} = SH{0};
let Inst{31} = rc;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
// 1.7.11 XO-Form
-class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
- bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
+class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
field bits<5> RT;
field bits<5> RA;
field bits<5> RB;
@@ -506,29 +513,27 @@
let Inst{21} = oe;
let Inst{22-30} = xo;
let Inst{31} = rc;
+ let OperandList = OL;
+ let AsmString = asmstr;
}
-// This is a reversal of the two operands, used notably by extended ops SUB*:
-// sub x, y, z == subf x, z, y
-// subc x, y, z == subfc x, z, y
-class XOForm_1_rev<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
- bit ppc64, bit vmx>
- : XOForm_1<name, opcode, xo, oe, rc, ppc64, vmx> {
+class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr>
+ : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
let Inst{11-15} = RB;
let Inst{16-20} = RA;
}
-class XOForm_2<string name, bits<6> opcode, bits<9> xo, bit rc, bit ppc64,
- bit vmx> : XOForm_1<name, opcode, xo, 0, rc, ppc64, vmx>;
-
-class XOForm_3<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
- bit ppc64, bit vmx> : XOForm_1<name,opcode,xo,oe,rc,ppc64,vmx> {
+class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr>
+ : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
+ let ArgCount = 2;
let RB = 0;
}
// 1.7.12 A-Form
-class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
- bit vmx, dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
+class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
+ dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
let ArgCount = 4;
field bits<5> FRT;
field bits<5> FRA;
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.30 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.31
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.30 Sun Aug 29 17:45:13 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Sun Aug 29 21:28:06 2004
@@ -17,42 +17,24 @@
let isTerminator = 1, isReturn = 1 in
def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
-class II<dag OL, string asmstr> {
- dag OperandList = OL;
- string AsmString = asmstr;
-}
-
def u5imm : Operand<i8> {
let PrintMethod = "printU5ImmOperand";
}
+def u6imm : Operand<i8> {
+ let PrintMethod = "printU6ImmOperand";
+}
def u16imm : Operand<i16> {
let PrintMethod = "printU16ImmOperand";
}
-
// Pseudo-instructions:
-def PHI : Pseudo<"PHI">; // PHI node...
+def PHI : Pseudo<"PHI">;
def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
let Defs = [LR] in
def MovePCtoLR : Pseudo<"MovePCtoLR">;
def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
-def LA : DForm_2<"la", 14, 0, 0>;
-def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
-
-def ADDI : DForm_2<"addi", 14, 0, 0>;
-def ADDIS : DForm_2<"addis", 15, 0, 0>;
-def SUBI : DForm_2<"subi", 14, 0, 0>;
-def LI : DForm_2_r0<"li", 14, 0, 0>;
-def LIS : DForm_2_r0<"lis", 15, 0, 0>;
-def ADDIC : DForm_2<"addic", 12, 0, 0>;
-def ADDICo : DForm_2<"addic.", 13, 0, 0>;
-def ADD : XOForm_1<"add", 31, 266, 0, 0, 0, 0>;
-def ADDC : XOForm_1<"addc", 31, 10, 0, 0, 0, 0>;
-def ADDE : XOForm_1<"adde", 31, 138, 0, 0, 0, 0>;
-def ADDZE : XOForm_3<"addze", 31, 202, 0, 0, 0, 0>;
-
let isBranch = 1, isTerminator = 1 in {
def COND_BRANCH : Pseudo<"COND_BRANCH">;
def B : IForm<"b", 18, 0, 0, 0, 0>;
@@ -77,111 +59,78 @@
def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
}
-def CMPI : DForm_5<"cmpi", 11, 0, 0>;
-def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
-def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
-def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
-def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
-def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
-def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
-def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
-def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
-def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
-def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
-def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
+def LA : DForm_2<"la", 14, 0, 0>;
+def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
+
def LBZ : DForm_1<"lbz", 35, 0, 0>;
def LHA : DForm_1<"lha", 42, 0, 0>;
def LHZ : DForm_1<"lhz", 40, 0, 0>;
-def LWZ : DForm_1<"lwz", 32, 0, 0>;
-def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
-def LD : DSForm_2<"ld", 58, 0, 1, 0>;
def LMW : DForm_1<"lmw", 46, 0, 0>;
-def STMW : DForm_3<"stmw", 47, 0, 0>;
-def LFS : DForm_8<"lfs", 48, 0, 0>;
-def LFD : DForm_8<"lfd", 50, 0, 0>;
-def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
- II<(ops GPRC:$reg), "mflr $reg">;
-def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
-def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
-def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
-def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
+def LWZ : DForm_1<"lwz", 32, 0, 0>;
+def ADDI : DForm_2<"addi", 14, 0, 0>;
+def ADDIC : DForm_2<"addic", 12, 0, 0>;
+def ADDICo : DForm_2<"addic.", 13, 0, 0>;
+def ADDIS : DForm_2<"addis", 15, 0, 0>;
def MULLI : DForm_2<"mulli", 7, 0, 0>;
-def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
-def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
-def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
-def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
-def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
-def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
-def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
-def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
-def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
-def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
-def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
+def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
+def SUBI : DForm_2<"subi", 14, 0, 0>;
+def LI : DForm_2_r0<"li", 14, 0, 0>;
+def LIS : DForm_2_r0<"lis", 15, 0, 0>;
+def STMW : DForm_3<"stmw", 47, 0, 0>;
def STB : DForm_3<"stb", 38, 0, 0>;
def STBU : DForm_3<"stbu", 39, 0, 0>;
def STH : DForm_3<"sth", 44, 0, 0>;
def STHU : DForm_3<"sthu", 45, 0, 0>;
def STW : DForm_3<"stw", 36, 0, 0>;
def STWU : DForm_3<"stwu", 37, 0, 0>;
-def STD : DSForm_2<"std", 62, 0, 1, 0>;
-def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
+def CMPI : DForm_5<"cmpi", 11, 0, 0>;
+def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
+def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
+def LFS : DForm_8<"lfs", 48, 0, 0>;
+def LFD : DForm_8<"lfd", 50, 0, 0>;
def STFS : DForm_9<"stfs", 52, 0, 0>;
def STFD : DForm_9<"stfd", 54, 0, 0>;
-def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
-def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
-def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
-def SUBC : XOForm_1_rev<"subc", 31, 8, 0, 0, 0, 0>;
-def SUBFC : XOForm_1<"subfc", 31, 8, 0, 0, 0, 0>;
-def SUBFE : XOForm_1<"subfe", 31, 136, 0, 0, 0, 0>;
-def SUBFZE : XOForm_3<"subfze", 31, 200, 0, 0, 0, 0>;
-def FMADD : AForm_1<63, 29, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmadd $FRT, $FRA, $FRC, $FRB">;
-def FSEL : AForm_1<63, 23, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB">;
-def FADD : AForm_2<63, 21, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadd $FRT, $FRA, $FRB">;
-def FADDS : AForm_2<59, 21, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadds $FRT, $FRA, $FRB">;
-def FDIV : AForm_2<63, 18, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdiv $FRT, $FRA, $FRB">;
-def FDIVS : AForm_2<59, 18, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdivs $FRT, $FRA, $FRB">;
-def FMUL : AForm_3<63, 25, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmul $FRT, $FRA, $FRB">;
-def FMULS : AForm_3<59, 25, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmuls $FRT, $FRA, $FRB">;
-def FSUB : AForm_2<63, 20, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsub $FRT, $FRA, $FRB">;
-def FSUBS : AForm_2<59, 20, 0, 0, 0,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsubs $FRT, $FRA, $FRB">;
+def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
+def LD : DSForm_2<"ld", 58, 0, 1, 0>;
+def STD : DSForm_2<"std", 62, 0, 1, 0>;
+def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
+def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
+def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
+def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
+def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
+def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
+def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
+
+def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
+def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
+def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
+def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
+def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
+def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
+def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
+
+// D-Form instructions. Most instructions that perform an operation on a
+// register and an immediate are of this type.
+//
def ANDIo : DForm_4<28, 0, 0,
- (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "andi. $dst, $src1, $src2">;
-def ORI : DForm_4<24, 0, 0,
- (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "ori $dst, $src1, $src2">;
-def ORIS : DForm_4<25, 0, 0,
- (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "oris $dst, $src1, $src2">;
+ (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
+ "andi. $dst, $src1, $src2">;
+def ORI : DForm_4<24, 0, 0,
+ (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
+ "ori $dst, $src1, $src2">;
+def ORIS : DForm_4<25, 0, 0,
+ (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
+ "oris $dst, $src1, $src2">;
def XORI : DForm_4<26, 0, 0,
- (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xori $dst, $src1, $src2">;
+ (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
+ "xori $dst, $src1, $src2">;
def XORIS : DForm_4<27, 0, 0,
- (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xoris $dst, $src1, $src2">;
-def CMPLI : DForm_6<10, 0, 0,
+ (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
+ "xoris $dst, $src1, $src2">;
+def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
+def CMPLI : DForm_6<10, 0, 0,
(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
"cmpli $dst, $size, $src1, $src2">;
def CMPLWI : DForm_6_ext<10, 0, 0,
@@ -191,6 +140,9 @@
(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
"cmpldi $dst, $src1, $src2">;
+// X-Form instructions. Most instructions that perform an operation on a
+// register and another register are of this type.
+//
def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"lbzx $dst, $base, $index">;
def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
@@ -277,6 +229,8 @@
def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
"stfdx $frS, $rA, $rB">;
+// XL-Form instructions. condition register logical ops.
+//
def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
"crand $D, $A, $B">;
def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
@@ -285,3 +239,86 @@
"crnor $D, $A, $B">;
def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
"cror $D, $A, $B">;
+
+// XFX-Form instructions. Instructions that deal with SPRs
+//
+def MFCTR : XFXForm_1_ext<31, 399, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
+def MFLR : XFXForm_1_ext<31, 399, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
+def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
+def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
+
+
+// XS-Form instructions. Just 'sradi'
+//
+def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
+ "sradi $rA, $rS, $SH">;
+
+// XO-Form instructions. Arithmetic instructions that can set overflow bit
+//
+def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "add $rT, $rA, $rB">;
+def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "addc $rT, $rA, $rB">;
+def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "adde $rT, $rA, $rB">;
+def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "divw $rT, $rA, $rB">;
+def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "divwu $rT, $rA, $rB">;
+def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "mulhwu $rT, $rA, $rB">;
+def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "mulld $rT, $rA, $rB">;
+def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "mullw $rT, $rA, $rB">;
+def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "subf $rT, $rA, $rB">;
+def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "subfc $rT, $rA, $rB">;
+def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "subfe $rT, $rA, $rB">;
+def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "sub $rT, $rA, $rB">;
+def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "subc $rT, $rA, $rB">;
+def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
+ "addze $rT, $rA">;
+def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
+ "neg $rT, $rA">;
+def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
+ "subfze $rT, $rA">;
+
+// A-Form instructions. Most of the instructions executed in the FPU are of
+// this type.
+//
+def FMADD : AForm_1<63, 29, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ "fmadd $FRT, $FRA, $FRC, $FRB">;
+def FSEL : AForm_1<63, 23, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB">;
+def FADD : AForm_2<63, 21, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fadd $FRT, $FRA, $FRB">;
+def FADDS : AForm_2<59, 21, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fadds $FRT, $FRA, $FRB">;
+def FDIV : AForm_2<63, 18, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fdiv $FRT, $FRA, $FRB">;
+def FDIVS : AForm_2<59, 18, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fdivs $FRT, $FRA, $FRB">;
+def FMUL : AForm_3<63, 25, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fmul $FRT, $FRA, $FRB">;
+def FMULS : AForm_3<59, 25, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fmuls $FRT, $FRA, $FRB">;
+def FSUB : AForm_2<63, 20, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fsub $FRT, $FRA, $FRB">;
+def FSUBS : AForm_2<59, 20, 0, 0, 0,
+ (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ "fsubs $FRT, $FRA, $FRB">;
+
More information about the llvm-commits
mailing list