[llvm-commits] CVS: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/Skeleton:

SkeletonRegisterInfo.td updated: 1.1 -> 1.2
---
Log message:

Register sizes should be specified in bits

---
Diffs of the changes:  (+2 -2)

Index: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
diff -u llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.1 llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.2
--- llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.1	Fri Jul 16 01:29:19 2004
+++ llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td	Sun Aug 29 17:03:40 2004
@@ -77,10 +77,10 @@
 
 /// Register classes: one for floats and another for non-floats.
 ///
-def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
+def GPRC : RegisterClass<i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
   R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
   R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
-def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;