[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td PPC64RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.td updated: 1.2 -> 1.3
PPC64RegisterInfo.td updated: 1.2 -> 1.3
---
Log message:

Switch from bytes to bits for alignment.
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit


---
Diffs of the changes:  (+6 -6)

Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.2 llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.3
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.2	Tue Aug 17 02:17:44 2004
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.td	Sat Aug 21 15:14:40 2004
@@ -15,7 +15,7 @@
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i32, 8,
+def GPRC : RegisterClass<i32, 32,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@
   }];
 }
 
-def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
+def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;


Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.2 llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.3
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.2	Tue Aug 17 02:17:44 2004
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.td	Sat Aug 21 15:14:40 2004
@@ -15,7 +15,7 @@
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i64, 8,
+def GPRC : RegisterClass<i64, 64,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@
   }];
 }
 
-def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
+def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;