[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.td updated: 1.2 -> 1.3
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Log message:

Convert regclass alignment from bytes to bites


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Diffs of the changes:  (+1 -1)

Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.2 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.3
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.2	Tue Aug 10 15:28:13 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Sat Aug 21 15:13:09 2004
@@ -35,7 +35,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;