[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp

[Misha Brukman]

Changes in directory llvm/lib/Target/PowerPC:

PPC64RegisterInfo.cpp updated: 1.1 -> 1.2
---
Log message:

Wrap long lines.


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Diffs of the changes:  (+5 -4)

Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.1 llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.1	Mon Aug 16 23:57:37 2004
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp	Thu Aug 19 11:28:30 2004
@@ -72,11 +72,10 @@
 PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
   };
-
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
   unsigned OC = Opcode[getIdx(RC)];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
@@ -204,13 +203,15 @@
     // convert into indexed form of the instruction
     // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
     // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
-    unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
+    unsigned NewOpcode = 
+      const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
     assert(NewOpcode && "No indexed form of load or store available!");
     MI.setOpcode(NewOpcode);
     MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
     MI.SetMachineOperandReg(2, PPC::R0);
   } else {
-    MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
+    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
+                              Offset);
   }
 }