[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9Instr.def SparcV9InstrInfo.h

[Brian Gaeke]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9Instr.def updated: 1.27 -> 1.28
SparcV9InstrInfo.h updated: 1.9 -> 1.10
---
Log message:

The SparcV9 target no longer uses any pseudoinstructions (SETSW, SETUW,
SETX) or M_PSEUDO_FLAG.


---
Diffs of the changes:  (+1 -9)

Index: llvm/lib/Target/SparcV9/SparcV9Instr.def
diff -u llvm/lib/Target/SparcV9/SparcV9Instr.def:1.27 llvm/lib/Target/SparcV9/SparcV9Instr.def:1.28
--- llvm/lib/Target/SparcV9/SparcV9Instr.def:1.27	Thu Jul  1 23:57:37 2004
+++ llvm/lib/Target/SparcV9/SparcV9Instr.def	Wed Aug 18 12:44:16 2004
@@ -49,13 +49,6 @@
 
 I(NOP, "nop",		0,  -1,  0, false, 0,  1,  SPARC_NONE,  M_NOP_FLAG)
 
-// Synthetic SPARC assembly opcodes for setting a register to a constant.
-// Max immediate constant should be ignored for both these instructions.
-// Use a latency > 1 since this may generate as many as 3 instructions.
-I(SETSW, "setsw",	2,   1,  0, true , 0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )
-I(SETUW, "setuw",	2,   1,  0, false, 0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )
-I(SETX,  "setx",	3,   2,  0, true,  0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )
-
 // Set high-order bits of register and clear low-order bits
 I(SETHI, "sethi",	2,  1, B22, false, 0,  1,  SPARC_IEUN,  0)
 


Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.9 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.10
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.9	Wed Aug  4 02:29:28 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h	Wed Aug 18 12:44:16 2004
@@ -50,8 +50,7 @@
       // last store opcode
       assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
 
-      if (opCode == V9::SETSW || opCode == V9::SETUW ||
-          opCode == V9::SETX  || opCode == V9::SETHI)
+      if (opCode == V9::SETHI)
         return 0;
       if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
         return 2;