[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC64.td PPC64InstrInfo.cpp PPC64InstrInfo.h PPC64RegisterInfo.cpp PPC64RegisterInfo.h PPC64RegisterInfo.td PPC64AsmPrinter.cpp PPC64ISelSimple.cpp PPC64TargetMachine.h
Misha Brukman
brukman at cs.uiuc.edu
Mon Aug 16 21:57:47 PDT 2004
Changes in directory llvm/lib/Target/PowerPC:
PPC64.td added (r1.1)
PPC64InstrInfo.cpp added (r1.1)
PPC64InstrInfo.h added (r1.1)
PPC64RegisterInfo.cpp added (r1.1)
PPC64RegisterInfo.h added (r1.1)
PPC64RegisterInfo.td added (r1.1)
PPC64AsmPrinter.cpp updated: 1.5 -> 1.6
PPC64ISelSimple.cpp updated: 1.4 -> 1.5
PPC64TargetMachine.h updated: 1.2 -> 1.3
---
Log message:
PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC
---
Diffs of the changes: (+592 -27)
Index: llvm/lib/Target/PowerPC/PPC64.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64.td:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64.td Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,43 ----
+ //===- PPC64.td - Describe the PowerPC64 Target Machine ----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ // Get the target-independent interfaces which we are implementing...
+ //
+ include "../Target.td"
+
+ //===----------------------------------------------------------------------===//
+ // Register File Description
+ //===----------------------------------------------------------------------===//
+
+ include "PPC32RegisterInfo.td"
+ include "PowerPCInstrInfo.td"
+
+ def PowerPCInstrInfo : InstrInfo {
+ let PHIInst = PHI;
+
+ let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type",
+ "Arg3Type", "Arg4Type", "VMX", "PPC64"];
+ let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+ }
+
+ def PPC64 : Target {
+ // Pointers on PPC64 are 64-bits in size.
+ let PointerType = i64;
+
+ let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+ R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+ F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+ F30, F31, CR2, CR3, CR4, LR];
+
+ // Pull in Instruction Info:
+ let InstructionSet = PowerPCInstrInfo;
+ }
Index: llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,59 ----
+ //===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "PowerPC.h"
+ #include "PPC64InstrInfo.h"
+ #include "PPC64GenInstrInfo.inc"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include <iostream>
+ using namespace llvm;
+
+ PPC64InstrInfo::PPC64InstrInfo()
+ : TargetInstrInfo(PPC64Insts, sizeof(PPC64Insts)/sizeof(PPC64Insts[0])) { }
+
+ bool PPC64InstrInfo::isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ MachineOpCode oc = MI.getOpcode();
+ if (oc == PPC::OR) { // or r1, r2, r2
+ assert(MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ MI.getOperand(2).isRegister() &&
+ "invalid PPC OR instruction!");
+ if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ } else if (oc == PPC::ADDI) { // addi r1, r2, 0
+ assert(MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(2).isImmediate() &&
+ "invalid PPC ADDI instruction!");
+ if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ } else if (oc == PPC::FMR) { // fmr r1, r2
+ assert(MI.getNumOperands() == 2 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ "invalid PPC FMR instruction");
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ return false;
+ }
Index: llvm/lib/Target/PowerPC/PPC64InstrInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64InstrInfo.h:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64InstrInfo.h Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,56 ----
+ //===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC64 implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPC64_INSTRUCTIONINFO_H
+ #define POWERPC64_INSTRUCTIONINFO_H
+
+ #include "PowerPCInstrInfo.h"
+ #include "PPC64RegisterInfo.h"
+
+ namespace llvm {
+
+ class PPC64InstrInfo : public TargetInstrInfo {
+ const PPC64RegisterInfo RI;
+ public:
+ PPC64InstrInfo();
+
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
+ /// such, whenever a client has an instance of instruction info, it should
+ /// always be able to get register info as well (through this method).
+ ///
+ virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+
+ //
+ // Return true if the instruction is a register to register move and
+ // leave the source and dest operands in the passed parameters.
+ //
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const;
+
+ static unsigned invertPPCBranchOpcode(unsigned Opcode) {
+ switch (Opcode) {
+ default: assert(0 && "Unknown PPC branch opcode!");
+ case PPC::BEQ: return PPC::BNE;
+ case PPC::BNE: return PPC::BEQ;
+ case PPC::BLT: return PPC::BGE;
+ case PPC::BGE: return PPC::BLT;
+ case PPC::BGT: return PPC::BLE;
+ case PPC::BLE: return PPC::BGT;
+ }
+ }
+ };
+
+ }
+
+ #endif
Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,317 ----
+ //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC64 implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #define DEBUG_TYPE "reginfo"
+ #include "PowerPC.h"
+ #include "PowerPCInstrBuilder.h"
+ #include "PPC64RegisterInfo.h"
+ #include "llvm/Constants.h"
+ #include "llvm/Type.h"
+ #include "llvm/CodeGen/ValueTypes.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/MachineFrameInfo.h"
+ #include "llvm/Target/TargetFrameInfo.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/TargetOptions.h"
+ #include "Support/CommandLine.h"
+ #include "Support/Debug.h"
+ #include "Support/STLExtras.h"
+ #include <cstdlib>
+ #include <iostream>
+ using namespace llvm;
+
+ namespace llvm {
+ // Switch toggling compilation for AIX
+ extern cl::opt<bool> AIX;
+ }
+
+ PPC64RegisterInfo::PPC64RegisterInfo()
+ : PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
+ ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
+ ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
+ ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
+ ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
+ ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
+ ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
+ ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
+ ImmToIdxMap[PPC::ADDI] = PPC::ADD;
+ }
+
+ static unsigned getIdx(const TargetRegisterClass *RC) {
+ if (RC == PPC64::GPRCRegisterClass) {
+ switch (RC->getSize()) {
+ default: assert(0 && "Invalid data size!");
+ case 1: return 0;
+ case 2: return 1;
+ case 4: return 2;
+ case 8: return 3;
+ }
+ } else if (RC == PPC64::FPRCRegisterClass) {
+ switch (RC->getSize()) {
+ default: assert(0 && "Invalid data size!");
+ case 4: return 4;
+ case 8: return 5;
+ }
+ }
+ std::cerr << "Invalid register class to getIdx()!\n";
+ abort();
+ }
+
+ void
+ PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, int FrameIdx) const {
+ const TargetRegisterClass *RC = getRegClass(SrcReg);
+ static const unsigned Opcode[] = {
+ PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
+ };
+
+ unsigned OC = Opcode[getIdx(RC)];
+ if (SrcReg == PPC::LR) {
+ BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
+ } else {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
+ }
+ }
+
+ void
+ PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx) const{
+ static const unsigned Opcode[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
+ };
+ const TargetRegisterClass *RC = getRegClass(DestReg);
+ unsigned OC = Opcode[getIdx(RC)];
+ if (DestReg == PPC::LR) {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
+ BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
+ } else {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
+ }
+ }
+
+ void PPC64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const {
+ MachineInstr *I;
+
+ if (RC == PPC64::GPRCRegisterClass) {
+ BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (RC == PPC64::FPRCRegisterClass) {
+ BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
+ } else {
+ std::cerr << "Attempt to copy register that is not GPR or FPR";
+ abort();
+ }
+ }
+
+ //===----------------------------------------------------------------------===//
+ // Stack Frame Processing methods
+ //===----------------------------------------------------------------------===//
+
+ // hasFP - Return true if the specified function should have a dedicated frame
+ // pointer register. This is true if the function has variable sized allocas or
+ // if frame pointer elimination is disabled.
+ //
+ static bool hasFP(MachineFunction &MF) {
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ return MFI->hasVarSizedObjects();
+ }
+
+ void PPC64RegisterInfo::
+ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
+ if (hasFP(MF)) {
+ // If we have a frame pointer, convert as follows:
+ // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
+ // ADJCALLSTACKUP -> addi, r1, r1, amount
+ MachineInstr *Old = I;
+ unsigned Amount = Old->getOperand(0).getImmedValue();
+ if (Amount != 0) {
+ // We need to keep the stack aligned properly. To do this, we round the
+ // amount of space needed for the outgoing arguments up to the next
+ // alignment boundary.
+ unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+ Amount = (Amount+Align-1)/Align*Align;
+
+ // Replace the pseudo instruction with a new instruction...
+ if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
+ MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
+ .addSImm(-Amount));
+ } else {
+ assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
+ MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
+ .addSImm(Amount));
+ }
+ }
+ }
+ MBB.erase(I);
+ }
+
+ void
+ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+ unsigned i = 0;
+ MachineInstr &MI = *II;
+ MachineBasicBlock &MBB = *MI.getParent();
+ MachineFunction &MF = *MBB.getParent();
+
+ while (!MI.getOperand(i).isFrameIndex()) {
+ ++i;
+ assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
+ }
+
+ int FrameIndex = MI.getOperand(i).getFrameIndex();
+
+ // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
+ MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
+
+ // Take into account whether it's an add or mem instruction
+ unsigned OffIdx = (i == 2) ? 1 : 2;
+
+ // Now add the frame object offset to the offset from r1.
+ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
+ MI.getOperand(OffIdx).getImmedValue();
+
+ // If we're not using a Frame Pointer that has been set to the value of the
+ // SP before having the stack size subtracted from it, then add the stack size
+ // to Offset to get the correct offset.
+ Offset += MF.getFrameInfo()->getStackSize();
+
+ if (Offset > 32767 || Offset < -32768) {
+ // Insert a set of r0 with the full offset value before the ld, st, or add
+ MachineBasicBlock *MBB = MI.getParent();
+ MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
+ MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(Offset));
+ // convert into indexed form of the instruction
+ // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
+ // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
+ unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
+ assert(NewOpcode && "No indexed form of load or store available!");
+ MI.setOpcode(NewOpcode);
+ MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
+ MI.SetMachineOperandReg(2, PPC::R0);
+ } else {
+ MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
+ }
+ }
+
+
+ void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
+ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
+ MachineBasicBlock::iterator MBBI = MBB.begin();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineInstr *MI;
+
+ // Get the number of bytes to allocate from the FrameInfo
+ unsigned NumBytes = MFI->getStackSize();
+
+ // If we have calls, we cannot use the red zone to store callee save registers
+ // and we must set up a stack frame, so calculate the necessary size here.
+ if (MFI->hasCalls()) {
+ // We reserve argument space for call sites in the function immediately on
+ // entry to the current function. This eliminates the need for add/sub
+ // brackets around call sites.
+ NumBytes += MFI->getMaxCallFrameSize();
+ }
+
+ // Do we need to allocate space on the stack?
+ if (NumBytes == 0) return;
+
+ // Add the size of R1 to NumBytes size for the store of R1 to the bottom
+ // of the stack and round the size to a multiple of the alignment.
+ unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+ unsigned R1Size = getRegClass(PPC::R1)->getSize();
+ unsigned R31Size = getRegClass(PPC::R31)->getSize();
+ unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size;
+ NumBytes = (NumBytes+Size+Align-1)/Align*Align;
+
+ // Update frame info to pretend that this is part of the stack...
+ MFI->setStackSize(NumBytes);
+
+ // adjust stack pointer: r1 -= numbytes
+ if (NumBytes <= 32768) {
+ MI=BuildMI(PPC::STDU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ } else {
+ int NegNumbytes = -NumBytes;
+ MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes & 0xFFFF);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ MBB.insert(MBBI, MI);
+ }
+
+ if (hasFP(MF)) {
+ MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ }
+ }
+
+ void PPC64RegisterInfo::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ MachineInstr *MI;
+ assert(MBBI->getOpcode() == PPC::BLR &&
+ "Can only insert epilog into returning blocks");
+
+ // Get the number of bytes allocated from the FrameInfo...
+ unsigned NumBytes = MFI->getStackSize();
+
+ if (NumBytes != 0) {
+ if (hasFP(MF)) {
+ MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::LD, 2, PPC::R31).addSImm(4).addReg(PPC::R31);
+ MBB.insert(MBBI, MI);
+ }
+ MI = BuildMI(PPC::LD, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ }
+ }
+
+ #include "PPC64GenRegisterInfo.inc"
+
+ const TargetRegisterClass*
+ PPC64RegisterInfo::getRegClassForType(const Type* Ty) const {
+ switch (Ty->getTypeID()) {
+ default: assert(0 && "Invalid type to getClass!");
+ case Type::BoolTyID:
+ case Type::SByteTyID:
+ case Type::UByteTyID:
+ case Type::ShortTyID:
+ case Type::UShortTyID:
+ case Type::IntTyID:
+ case Type::UIntTyID:
+ case Type::PointerTyID:
+ case Type::LongTyID:
+ case Type::ULongTyID: return &GPRCInstance;
+
+ case Type::FloatTyID:
+ case Type::DoubleTyID: return &FPRCInstance;
+ }
+ }
+
Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.h:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.h Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,56 ----
+ //===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPC64_REGISTERINFO_H
+ #define POWERPC64_REGISTERINFO_H
+
+ #include "PowerPC.h"
+ #include "PPC64GenRegisterInfo.h.inc"
+ #include <map>
+
+ namespace llvm {
+
+ class Type;
+
+ class PPC64RegisterInfo : public PPC64GenRegisterInfo {
+ std::map<unsigned, unsigned> ImmToIdxMap;
+ public:
+ PPC64RegisterInfo();
+ const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+
+ /// Code Generation virtual methods...
+ void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIndex) const;
+
+ void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex) const;
+
+ void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const;
+
+ void eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const;
+
+ void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+
+ void emitPrologue(MachineFunction &MF) const;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ };
+
+ } // end namespace llvm
+
+ #endif
Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.1
*** /dev/null Mon Aug 16 23:57:47 2004
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td Mon Aug 16 23:57:37 2004
***************
*** 0 ****
--- 1,40 ----
+ //===- PPC64RegisterInfo.td - The PowerPC64 Register File --*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ include "PowerPCRegisterInfo.td"
+
+ /// Register classes
+ // Allocate volatiles first
+ // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
+ def GPRC : RegisterClass<i64, 8,
+ [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+ R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+ R16, R15, R14, R13, R0, R1, LR]>
+ {
+ let Methods = [{
+ iterator allocation_order_begin(MachineFunction &MF) const {
+ return begin() + (AIX ? 1 : 0);
+ }
+ iterator allocation_order_end(MachineFunction &MF) const {
+ if (hasFP(MF))
+ return end()-4;
+ else
+ return end()-3;
+ }
+ }];
+ }
+
+ def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+ F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+ F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
+ def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
Index: llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.5 llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.6
--- llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.5 Sun Aug 15 00:48:47 2004
+++ llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp Mon Aug 16 23:57:37 2004
@@ -24,7 +24,6 @@
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "Support/CommandLine.h"
#include "Support/Debug.h"
Index: llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.4 llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.5
--- llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.4 Thu Aug 12 21:20:47 2004
+++ llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp Mon Aug 16 23:57:37 2004
@@ -377,10 +377,10 @@
/// yet used.
///
unsigned makeAnotherReg(const Type *Ty) {
- assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
+ assert(dynamic_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have PPC reg info??");
- const PowerPCRegisterInfo *PPCRI =
- static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
+ const PPC64RegisterInfo *PPCRI =
+ static_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo());
// Add the mapping of regnumber => reg class to MachineFunction
const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC);
@@ -1288,7 +1288,7 @@
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
- Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
+ Opcode = PPC64InstrInfo::invertPPCBranchOpcode(Opcode);
BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
@@ -1497,8 +1497,6 @@
}
// Emit a CALL instruction with PC-relative displacement.
TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
- // Add it to the set of functions called to be used by the Printer
- TM.CalledFunctions.insert(F);
} else { // Emit an indirect call through the CTR
unsigned Reg = getReg(CI.getCalledValue());
BuildMI(BB, PPC::MTCTR, 1).addReg(Reg);
@@ -1997,7 +1995,6 @@
Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
- TM.CalledFunctions.insert(fmodfFn);
}
return;
case cFP64:
@@ -2015,7 +2012,6 @@
Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
- TM.CalledFunctions.insert(fmodFn);
}
return;
case cLong: {
@@ -2031,7 +2027,6 @@
Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
- TM.CalledFunctions.insert(Funcs[NameIdx]);
return;
}
case cByte: case cShort: case cInt:
@@ -2401,7 +2396,6 @@
MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
- TM.CalledFunctions.insert(floatFn);
return;
}
@@ -2473,7 +2467,6 @@
MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
- TM.CalledFunctions.insert(floatFn);
return;
}
@@ -3041,7 +3034,6 @@
MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
- TM.CalledFunctions.insert(mallocFn);
}
@@ -3054,7 +3046,6 @@
MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
- TM.CalledFunctions.insert(freeFn);
}
/// createPPC64ISelSimple - This pass converts an LLVM function into a machine
Index: llvm/lib/Target/PowerPC/PPC64TargetMachine.h
diff -u llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.2 llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.3
--- llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.2 Wed Aug 11 02:40:04 2004
+++ llvm/lib/Target/PowerPC/PPC64TargetMachine.h Mon Aug 16 23:57:37 2004
@@ -1,4 +1,4 @@
-//===-- PPC64TargetMachine.h - Define AIX/PowerPC TargetMachine --*- C++ -*-=//
+//===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@@ -7,31 +7,35 @@
//
//===----------------------------------------------------------------------===//
//
-// This file declares the PowerPC/AIX specific subclass of TargetMachine.
+// This file declares the PowerPC specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
-#ifndef POWERPC_AIX_TARGETMACHINE_H
-#define POWERPC_AIX_TARGETMACHINE_H
+#ifndef POWERPC64_TARGETMACHINE_H
+#define POWERPC64_TARGETMACHINE_H
#include "PowerPCTargetMachine.h"
+#include "PPC64InstrInfo.h"
+#include "llvm/PassManager.h"
namespace llvm {
+class IntrinsicLowering;
+
class PPC64TargetMachine : public PowerPCTargetMachine {
+ PPC64InstrInfo InstrInfo;
+
public:
PPC64TargetMachine(const Module &M, IntrinsicLowering *IL);
+ virtual const PPC64InstrInfo *getInstrInfo() const { return &InstrInfo; }
+ virtual const MRegisterInfo *getRegisterInfo() const {
+ return &InstrInfo.getRegisterInfo();
+ }
- /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
- /// actually outputting the machine code and resolving things like the address
- /// of functions. This method should returns true if machine code emission is
- /// not supported.
- ///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE);
-
static unsigned getModuleMatchQuality(const Module &M);
+
+ bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE);
};
} // end namespace llvm
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