[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp RegAllocLocal.cpp RegAllocSimple.cpp VirtRegMap.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen:

PrologEpilogInserter.cpp updated: 1.30 -> 1.31
RegAllocLocal.cpp updated: 1.64 -> 1.65
RegAllocSimple.cpp updated: 1.58 -> 1.59
VirtRegMap.cpp updated: 1.16 -> 1.17
---
Log message:

These methods no longer take a TargetRegisterClass* operand.


---
Diffs of the changes:  (+11 -18)

Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.30 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.31
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.30	Sun Aug 15 04:17:00 2004
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp	Sun Aug 15 16:56:44 2004
@@ -206,10 +206,8 @@
   MachineBasicBlock *MBB = Fn.begin();
   MachineBasicBlock::iterator I = MBB->begin();
   for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
-    const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
-
-    // Insert the spill to the stack frame...
-    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i], RC);
+    // Insert the spill to the stack frame.
+    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
   }
 
   // Add code to restore the callee-save registers in each exiting block.
@@ -221,8 +219,7 @@
       I = MBB->end(); --I;
 
       for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
-        const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
-        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i], RC);
+        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i]);
         --I;  // Insert in reverse order
       }
     }


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.64 llvm/lib/CodeGen/RegAllocLocal.cpp:1.65
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.64	Wed Jul 21 15:50:33 2004
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Sun Aug 15 16:56:44 2004
@@ -267,7 +267,7 @@
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DEBUG(std::cerr << " to stack slot #" << FrameIndex);
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
     ++NumStores;   // Update statistics
   }
 
@@ -506,7 +506,7 @@
                   << RegInfo->getName(PhysReg) << "\n");
 
   // Add move instruction(s)
-  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
   ++NumLoads;    // Update statistics
 
   MI->SetMachineOperandReg(OpNum, PhysReg);  // Assign the input register


Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.58 llvm/lib/CodeGen/RegAllocSimple.cpp:1.59
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.58	Wed Jul 21 15:50:33 2004
+++ llvm/lib/CodeGen/RegAllocSimple.cpp	Sun Aug 15 16:56:44 2004
@@ -131,7 +131,7 @@
 
   // Add move instruction(s)
   ++NumLoads;
-  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
   return PhysReg;
 }
 
@@ -143,7 +143,7 @@
 
   // Add move instruction(s)
   ++NumStores;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
 }
 
 


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.16 llvm/lib/CodeGen/VirtRegMap.cpp:1.17
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.16	Wed Jul 21 15:50:33 2004
+++ llvm/lib/CodeGen/VirtRegMap.cpp	Sun Aug 15 16:56:44 2004
@@ -144,8 +144,7 @@
                                     *mbbi,
                                     mii,
                                     physReg,
-                                    vrm.getStackSlot(virtReg),
-                                    mf.getSSARegMap()->getRegClass(virtReg));
+                                    vrm.getStackSlot(virtReg));
                                 loaded[virtReg] = true;
                                 DEBUG(std::cerr << '\t';
                                       prior(mii)->print(std::cerr, &tm));
@@ -157,8 +156,7 @@
                                     *mbbi,
                                     next(mii),
                                     physReg,
-                                    vrm.getStackSlot(virtReg),
-                                    mf.getSSARegMap()->getRegClass(virtReg));
+                                    vrm.getStackSlot(virtReg));
                                 ++numStores;
                             }
                             mii->SetMachineOperandReg(i, physReg);
@@ -226,8 +224,7 @@
                 mri_->storeRegToStackSlot(*lastDef->getParent(),
                                           nextLastRef,
                                           physReg,
-                                          vrm_->getStackSlot(virtReg),
-                                          mri_->getRegClass(physReg));
+                                          vrm_->getStackSlot(virtReg));
                 ++numStores;
                 DEBUG(std::cerr << "added: ";
                       prior(nextLastRef)->print(std::cerr, tm_);
@@ -258,8 +255,7 @@
                 // load if necessary
                 if (vrm_->hasStackSlot(virtReg)) {
                     mri_->loadRegFromStackSlot(mbb, mii, physReg,
-                                               vrm_->getStackSlot(virtReg),
-                                               mri_->getRegClass(physReg));
+                                               vrm_->getStackSlot(virtReg));
                     ++numLoads;
                     DEBUG(std::cerr << "added: ";
                           prior(mii)->print(std::cerr, tm_));