[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td PowerPCInstrInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrFormats.td updated: 1.11 -> 1.12
PowerPCInstrInfo.td updated: 1.19 -> 1.20
---
Log message:

Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files

---
Diffs of the changes:  (+57 -2)

Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.11 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.12
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.11	Wed Aug 11 15:56:14 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td	Thu Aug 12 21:19:25 2004
@@ -37,6 +37,7 @@
 def Sgr : Format<20>;
 def Imm15 : Format<21>;
 def Vpr : Format<22>;
+def Imm6 : Format<23>;
 
 //===----------------------------------------------------------------------===//
 //
@@ -266,6 +267,7 @@
   let Inst{31}    = rc;
 }
 
+
 class XForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, 
               bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
 
@@ -448,6 +450,28 @@
   let SPR = spr;
 }
 
+// 1.7.10 XS-Form
+class XSForm_1<string name, bits<6> opcode, bits<9> xo, bit rc, 
+                      bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
+  field bits<5> RS;
+  field bits<5> A;
+  field bits<6> SH;
+
+  let ArgCount = 3;
+  let Arg0Type = Gpr.Value;
+  let Arg1Type = Gpr.Value;
+  let Arg2Type = Imm6.Value;
+  let Arg3Type = 0;
+  let Arg4Type = 0;
+
+  let Inst{6-10}  = RS;
+  let Inst{11-15} = A;
+  let Inst{16-20} = SH{1-5};
+  let Inst{21-29} = xo;
+  let Inst{30}    = SH{0};
+  let Inst{31}    = rc;
+}
+
 // 1.7.11 XO-Form
 class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc, 
                bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
@@ -563,6 +587,30 @@
   let Arg2Type = Imm5.Value;
 }
 
+// 1.7.14 MD-Form
+class MDForm_1<string name, bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx> 
+  : I<name, opcode, ppc64, vmx> {
+  let ArgCount = 4;
+  field bits<5>  RS;
+  field bits<5>  RA;
+  field bits<6>  SH;
+  field bits<6>  MBE;
+
+  let Arg0Type = Gpr.Value;
+  let Arg1Type = Gpr.Value;
+  let Arg2Type = Imm6.Value;
+  let Arg3Type = Imm6.Value;
+  let Arg4Type = 0;
+
+  let Inst{6-10}  = RS;
+  let Inst{11-15} = RA;
+  let Inst{16-20} = SH{1-5};
+  let Inst{21-26} = MBE;
+  let Inst{27-29} = xo;
+  let Inst{30}    = SH{0};
+  let Inst{31}    = rc;
+}
+
 //===----------------------------------------------------------------------===//
 
 class Pseudo<string name> : I<name, 0, 0, 0> {


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.19 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.20
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.19	Wed Aug 11 18:33:34 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Thu Aug 12 21:19:26 2004
@@ -123,6 +123,7 @@
 def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
 def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
 def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
+def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
 def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
 def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
 def NAND  : XForm_6<"nand",  31, 476, 0, 0, 0>;
@@ -133,13 +134,19 @@
 def ORIS : DForm_4<"oris", 25, 0, 0>;
 def OR  : XForm_6<"or",  31, 444, 0, 0, 0>;
 def ORo : XForm_6<"or.", 31, 444, 1, 0, 0>;
+def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
+def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
 def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
 def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
 def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
+def SLD  : XForm_6<"sld",  31, 27, 0, 1, 0>;
 def SLW  : XForm_6<"slw",  31, 24, 0, 0, 0>;
-def SRW  : XForm_6<"srw",  31, 24, 0, 0, 0>;
+def SRD  : XForm_6<"srd",  31, 539, 0, 1, 0>;
+def SRW  : XForm_6<"srw",  31, 536, 0, 0, 0>;
+def SRADI  : XSForm_1<"sradi",  31, 413, 0, 1, 0>;
 def SRAWI  : XForm_10<"srawi",  31, 824, 0, 0, 0>;
-def SRAW  : XForm_6<"sraw",  31, 280, 0, 0, 0>;
+def SRAD  : XForm_6<"srad",  31, 794, 0, 1, 0>;
+def SRAW  : XForm_6<"sraw",  31, 792, 0, 0, 0>;
 def STB : DForm_3<"stb", 38, 0, 0>;
 def STBU : DForm_3<"stbu", 39, 0, 0>;
 def STBX : XForm_8<"stbx", 31, 215, 0, 0>;