[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86AsmPrinter.cpp updated: 1.112 -> 1.113
---
Log message:

Move hacks up


---
Diffs of the changes:  (+30 -32)

Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.112 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.113
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.112	Tue Aug 10 21:25:00 2004
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Wed Aug 11 01:09:55 2004
@@ -49,7 +49,6 @@
 
     ~GasBugWorkaroundEmitter() {
       O.flags(OldFlags);
-      O << "\t# ";
     }
 
     virtual void emitByte(unsigned char B) {
@@ -586,6 +585,36 @@
 ///
 void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   ++EmittedInsts;
+
+  // gas bugs:
+  //
+  // The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"  is misassembled
+  // by gas in intel_syntax mode as its 32-bit equivalent "fstp DWORD PTR
+  // [...]". Workaround: Output the raw opcode bytes instead of the instruction.
+  //
+  // The 80-bit FP load instruction "fld XWORD PTR [...]" is misassembled by gas
+  // in intel_syntax mode as its 32-bit equivalent "fld DWORD PTR
+  // [...]". Workaround: Output the raw opcode bytes instead of the instruction.
+  //
+  // gas intel_syntax mode treats "fild QWORD PTR [...]" as an invalid opcode,
+  // saying "64 bit operations are only supported in 64 bit modes." libopcodes
+  // disassembles it as "fild DWORD PTR [...]", which is wrong. Workaround:
+  // Output the raw opcode bytes instead of the instruction.
+  //
+  // gas intel_syntax mode treats "fistp QWORD PTR [...]" as an invalid opcode,
+  // saying "64 bit operations are only supported in 64 bit modes." libopcodes
+  // disassembles it as "fistpll DWORD PTR [...]", which is wrong. Workaround:
+  // Output the raw opcode bytes instead of the instruction.
+  switch (MI->getOpcode()) {
+  case X86::FSTP80m:
+  case X86::FLD80m:
+  case X86::FILD64m:
+  case X86::FISTP64m:
+    GasBugWorkaroundEmitter gwe(O);
+    X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
+    O << "\t# ";
+  }
+
   if (printInstruction(MI))
     return;   // Printer was automatically generated
 
@@ -853,37 +882,6 @@
 
     const MachineOperand &Op3 = MI->getOperand(3);
 
-    // gas bugs:
-    //
-    // The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"
-    // is misassembled by gas in intel_syntax mode as its 32-bit
-    // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
-    // opcode bytes instead of the instruction.
-    //
-    // The 80-bit FP load instruction "fld XWORD PTR [...]" is
-    // misassembled by gas in intel_syntax mode as its 32-bit
-    // equivalent "fld DWORD PTR [...]". Workaround: Output the raw
-    // opcode bytes instead of the instruction.
-    //
-    // gas intel_syntax mode treats "fild QWORD PTR [...]" as an
-    // invalid opcode, saying "64 bit operations are only supported in
-    // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
-    // [...]", which is wrong. Workaround: Output the raw opcode bytes
-    // instead of the instruction.
-    //
-    // gas intel_syntax mode treats "fistp QWORD PTR [...]" as an
-    // invalid opcode, saying "64 bit operations are only supported in
-    // 64 bit modes." libopcodes disassembles it as "fistpll DWORD PTR
-    // [...]", which is wrong. Workaround: Output the raw opcode bytes
-    // instead of the instruction.
-    if (MI->getOpcode() == X86::FSTP80m ||
-        MI->getOpcode() == X86::FLD80m ||
-        MI->getOpcode() == X86::FILD64m ||
-        MI->getOpcode() == X86::FISTP64m) {
-      GasBugWorkaroundEmitter gwe(O);
-      X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
-    }
-
     O << TII.getName(MI->getOpcode()) << " ";
     O << sizePtr(Desc) << " ";
     printMemReference(MI, 0);