[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td SparcV9_Reg.td

[Misha Brukman]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.td added (r1.1)
SparcV9_Reg.td (r1.9) removed
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Log message:

Renamed SparcV9_Reg.td -> SparcV9RegisterInfo.td for consistency.


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Diffs of the changes:  (+41 -0)

Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -c /dev/null llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.1
*** /dev/null	Tue Aug 10 13:14:14 2004
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Tue Aug 10 13:14:04 2004
***************
*** 0 ****
--- 1,41 ----
+ //===- SparcV9_Reg.td - SparcV9 Register definitions ----------------------===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ 
+ //===----------------------------------------------------------------------===//
+ //  Declarations that describe the SparcV9 register file 
+ //===----------------------------------------------------------------------===//
+ 
+ // Ri - One of the 32 64 bit integer registers
+ class Ri<bits<5> num> : Register {
+   field bits<5> Num = num;        // Numbers are identified with a 5 bit ID
+ }
+ 
+ let Namespace = "SparcV9" in {
+   def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
+   def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;
+   def O0 : Ri< 8>;    def O1 : Ri< 9>;    def O2 : Ri<10>;    def O3 : Ri<11>;
+   def O4 : Ri<12>;    def O5 : Ri<13>;    def O6 : Ri<14>;    def O7 : Ri<15>;
+   def L0 : Ri<16>;    def L1 : Ri<17>;    def L2 : Ri<18>;    def L3 : Ri<19>;
+   def L4 : Ri<20>;    def L5 : Ri<21>;    def L6 : Ri<22>;    def L7 : Ri<23>;
+   def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
+   def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
+   // Floating-point registers?
+   // ...
+ }
+ 
+ 
+ // For fun, specify a register class.
+ //
+ // FIXME: the register order should be defined in terms of the preferred
+ // allocation order...
+ //
+ def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+                                      O0, O1, O2, O3, O4, O5, O6, O7,
+                                      L0, L1, L2, L3, L4, L5, L6, L7,
+                                      I0, I1, I2, I3, I4, I5, I6, I7]>;