[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervals.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen:

LiveIntervals.cpp updated: 1.91 -> 1.92

---
Log message:

Two changes, both very significant:

* vreg <-> vreg joining now works, enable it unconditionally when joining
  is enabled (which is the default).
* Fix a serious pessimization of spill code where we were saying that a
  spilled DEF operand was live into the subsequent instruction.  This allows
  for substantially better code when spilling starts to happen.



---
Diffs of the changes:  (+2 -11)

Index: llvm/lib/CodeGen/LiveIntervals.cpp
diff -u llvm/lib/CodeGen/LiveIntervals.cpp:1.91 llvm/lib/CodeGen/LiveIntervals.cpp:1.92
--- llvm/lib/CodeGen/LiveIntervals.cpp:1.91	Mon Jul 19 00:15:10 2004
+++ llvm/lib/CodeGen/LiveIntervals.cpp	Mon Jul 19 00:55:50 2004
@@ -60,11 +60,6 @@
     EnableJoining("join-liveintervals",
                   cl::desc("Join compatible live intervals"),
                   cl::init(true));
-
-    cl::opt<bool>
-    EnableVirtVirtJoining("join-liveintervals-virtvirtjoining",
-                      cl::desc("Join live intervals for virtreg pairs (buggy)"),
-                          cl::init(false));
 };
 
 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
@@ -251,7 +246,7 @@
                         // use of the next instruction. Otherwise we end
                         // after the use of this instruction.
                         unsigned end = 1 + (mop.isDef() ?
-                                            getUseIndex(index+InstrSlots::NUM) :
+                                            getStoreIndex(index) :
                                             getUseIndex(index));
 
                         // create a new register for this spill
@@ -545,11 +540,7 @@
                 Intervals::iterator intB = r2iB->second;
 
                 // both A and B are virtual registers
-
-                // FIXME: coallescing two virtual registers together is
-                // apparently broken.
-                if (EnableVirtVirtJoining && 
-                    MRegisterInfo::isVirtualRegister(intA->reg) &&
+                if (MRegisterInfo::isVirtualRegister(intA->reg) &&
                     MRegisterInfo::isVirtualRegister(intB->reg)) {
 
                     const TargetRegisterClass *rcA, *rcB;