[llvm-commits] CVS: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp

[Brian Gaeke]

Changes in directory reopt/lib/LightWtProfiling:

UnpackTraceFunction.cpp updated: 1.96 -> 1.97

---
Log message:

Wrap long lines. No functional changes.


---
Diffs of the changes:  (+29 -20)

Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp
diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.96 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.97
--- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.96	Sun Jul 11 19:33:26 2004
+++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp	Mon Jul 12 01:21:33 2004
@@ -134,7 +134,9 @@
   DEBUG(std::cerr << "findRegsToSave: RegsToSave (size " 
         << RegsToSave.size () << ") contains: (";
         for (std::set<unsigned>::iterator i = RegsToSave.begin (),
-             e = RegsToSave.end (); i != e; ++i) { std::cerr << RegStr (*i) << " "; }
+             e = RegsToSave.end (); i != e; ++i) {
+          std::cerr << RegStr (*i) << " ";
+        }
         std::cerr << " )\n");
 }
 
@@ -148,7 +150,8 @@
   const SparcV9RegInfo &TRI = *TM->getRegInfo ();
   unsigned RegType = TRI.getRegType (R);
   const char *RegName = TRI.getUnifiedRegName (R);
-  return std::string("reg#")  + utostr(R) + "(" + RegTypeStrings[RegType] + ")=%" + RegName;
+  return std::string("reg#") + utostr(R) + "(" + RegTypeStrings[RegType]
+         + ")=%" + RegName;
 }
 
 void UnpackTraceFunction::PrintAI (const AllocInfo &AI) const {
@@ -156,7 +159,8 @@
     case AllocInfo::Allocated:
       std::cerr << "allocated to " << RegStr (AI.Placement); return;
     case AllocInfo::Spilled:
-      std::cerr << "spilled at 0x" << std::hex << AI.Placement << std::dec; return;
+      std::cerr << "spilled at 0x" << std::hex << AI.Placement << std::dec;
+      return;
     case AllocInfo::NotAllocated:
       std::cerr << "not allocated"; return;
   }
@@ -202,7 +206,8 @@
     mvec.clear ();
     unsigned R = *i;
     DEBUG (std::cerr << "rewriteProlog: Saving " << RegStr (R) << "\n");
-    TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2);
+    TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R),
+                     g2);
     for (std::vector<MachineInstr *>::iterator vi = mvec.begin (),
            ve = mvec.end (); vi != ve; ++vi)
       E.push_back (*vi);
@@ -263,12 +268,14 @@
   }
 }
 
-static void regAllocConstORi (std::vector<MachineInstr *> &mvec, unsigned DestReg, unsigned SpareReg) { 
+static void regAllocConstORi (std::vector<MachineInstr *> &mvec,
+                              unsigned DestReg, unsigned SpareReg) { 
   MachineInstr &theInst = *mvec.back();
   assert (theInst.getOpcode () == V9::ORi
           && theInst.getNumOperands () == 3
           && theInst.getOperand (2).isDef ()
-          && theInst.getOperand (2).getType () == MachineOperand::MO_VirtualRegister
+          && theInst.getOperand (2).getType ()
+             == MachineOperand::MO_VirtualRegister
           && "wrong machineInstr passed to regAllocConstORi");
   theInst.SetRegForOperand (2, DestReg);
 }
@@ -290,7 +297,7 @@
   for (std::vector<MachineInstr *>::iterator i = mvec.begin (),
        e = mvec.end(); i != e; ++i) {
     MachineInstr &MInst = **i;
-    for (unsigned opNum=0, nOps=MInst.getNumOperands (); opNum != nOps;
+    for (unsigned opNum = 0, nOps = MInst.getNumOperands (); opNum != nOps;
          ++opNum) {
       MachineOperand &Op = MInst.getOperand (opNum);
       if (Op.getType() == MachineOperand::MO_VirtualRegister) {
@@ -307,21 +314,23 @@
   }
 }
 
-void UnpackTraceFunction::copyConstantToRegister (MachineFunction &MF,
-                                                  Constant *C, unsigned Reg,
-                                                  unsigned SpareReg,
-                                                  std::vector<MachineInstr *> &mvec) {
+void
+UnpackTraceFunction::copyConstantToRegister (MachineFunction &MF, Constant *C,
+                                             unsigned Reg, unsigned SpareReg,
+                                             std::vector<MachineInstr *> &mvec){
   const TargetInstrInfo &TII = *TM->getInstrInfo ();
   TmpInstruction *tmp = new TmpInstruction (C);
   MachineCodeForInstruction throwaway;
-  TII.CreateCodeToLoadConst (*TM, const_cast<Function *> (MF.getFunction ()), C, tmp, mvec, throwaway);
+  TII.CreateCodeToLoadConst (*TM, const_cast<Function *> (MF.getFunction ()),
+                             C, tmp, mvec, throwaway);
                              
-  DEBUG (for (std::vector<MachineInstr *>::iterator i = mvec.begin (), e = mvec.end ();
-              i != e; ++i)
-         std::cerr << "copyConstantToRegister Input: " << **i << "\n");
+  DEBUG (for (std::vector<MachineInstr *>::iterator i = mvec.begin (),
+              e = mvec.end (); i != e; ++i)
+           std::cerr << "copyConstantToRegister Input: " << **i << "\n");
          
-  // note: this is pretty seriously hardwired for now. the problem is that in full
-  // generality, this is a little tiny episode of register allocation
+  // note: this is pretty seriously hardwired for now. the problem is
+  // that in full generality, this is a little tiny episode of register
+  // allocation
   if (mvec.size() == 1 && mvec.back()->getOpcode() == V9::ORi) {
     regAllocConstORi (mvec,Reg,SpareReg);
   } else if (mvec.size() == 7 && mvec.back()->getOpcode() == V9::LDDFi) {
@@ -330,9 +339,9 @@
     assert (0 && "unknown sequence coming out of CreateCodeToLoadConst");
   }
   
-  DEBUG (for (std::vector<MachineInstr *>::iterator i = mvec.begin (), e = mvec.end ();
-              i != e; ++i)
-         std::cerr << "copyConstantToRegister Output: " << **i << "\n");
+  DEBUG (for (std::vector<MachineInstr *>::iterator i = mvec.begin (),
+              e = mvec.end (); i != e; ++i)
+           std::cerr << "copyConstantToRegister Output: " << **i << "\n");
 }
 
 /// addLiveOutCopy - Add a copy of the Value which is liveOutValue in the