[llvm-commits] CVS: llvm/docs/LangRef.html

John Criswell criswell at cs.uiuc.edu
Fri Jun 25 10:18:01 PDT 2004

Changes in directory llvm/docs:

LangRef.html updated: 1.67 -> 1.68

Log message:

Added missing quote.

Diffs of the changes:  (+48 -2)

Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.67 llvm/docs/LangRef.html:1.68
--- llvm/docs/LangRef.html:1.67	Mon Jun 21 17:52:48 2004
+++ llvm/docs/LangRef.html	Fri Jun 25 10:16:57 2004
@@ -764,7 +764,7 @@
 <p>When the '<tt>ret</tt>' instruction is executed, control flow
 returns back to the calling function's context.  If the caller is a "<a
- href="#i_call"><tt>call</tt></a> instruction, execution continues at
+ href="#i_call"><tt>call</tt></a>" instruction, execution continues at
 the instruction after the call.  If the caller was an "<a
  href="#i_invoke"><tt>invoke</tt></a>" instruction, execution continues
 at the beginning "normal" of the destination block.  If the instruction
@@ -2357,6 +2357,52 @@
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="i_interrupt_handler">'<tt>llvm.interrupt_handler</tt>' Intrinsic</a>
+<div class="doc_text">
+  call void (void)* %llvm.interrupt_handler (void)
+The '<tt>llvm.interrupt_handler</tt>' intrinsic installs the specified function
+as an interrupt handler for the specified interrupt.
+The first argument is the value to write to the memory mapped I/O location.
+The second argument is a pointer indicating the memory address to which the
+data should be written.
+The '<tt>llvm.writeio</tt>' intrinsic writes <i>value</i> to the memory mapped
+I/O address specified by <i>pointer</i>.  The value must be a
+<a href="#t_firstclass">first class</a> type.  However, certain architectures
+may not support I/O on all first class types.  For example, 32 bit processors
+may only support I/O on data types that are 32 bits or less.
+This intrinsic enforces an in-order memory model for llvm.readio and
+llvm.writeio calls on machines that use dynamic scheduling.  Dynamically
+scheduled processors may execute loads and stores out of order, re-ordering at
+run time accesses to memory mapped I/O registers.  Using these intrinsics
+ensures that accesses to memory mapped I/O registers occur in program order.
 <!-- ======================================================================= -->
 <div class="doc_subsection">
@@ -2591,7 +2637,7 @@
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2004/06/21 22:52:48 $
+  Last modified: $Date: 2004/06/25 15:16:57 $

More information about the llvm-commits mailing list