[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/InstrSched:

InstrScheduling.cpp updated: 1.70 -> 1.71
SchedGraph.cpp updated: 1.60 -> 1.61

---
Log message:

Adjust to the new TargetMachine interface


---
Diffs of the changes:  (+16 -16)

Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.70 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.71
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.70	Wed Mar 31 15:59:43 2004
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp	Wed Jun  2 01:06:19 2004
@@ -512,15 +512,15 @@
 SchedulingManager::SchedulingManager(const TargetMachine& target,
 				     const SchedGraph* graph,
 				     SchedPriorities& _schedPrio)
-  : nslots(target.getSchedInfo().getMaxNumIssueTotal()),
-    schedInfo(target.getSchedInfo()),
+  : nslots(target.getSchedInfo()->getMaxNumIssueTotal()),
+    schedInfo(*target.getSchedInfo()),
     schedPrio(_schedPrio),
     isched(nslots, graph->getNumNodes()),
     totalInstrCount(graph->getNumNodes() - 2),
     nextEarliestIssueTime(0),
     choicesForSlot(nslots),
-    numInClass(target.getSchedInfo().getNumSchedClasses(), 0),	// set all to 0
-    nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(),
+    numInClass(target.getSchedInfo()->getNumSchedClasses(), 0),	// set all to 0
+    nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(),
 			  (cycles_t) 0)				// set all to 0
 {
   updateTime(0);


Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.60 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.61
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.60	Fri Apr 23 13:15:46 2004
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp	Wed Jun  2 01:06:20 2004
@@ -60,9 +60,9 @@
     MI = I;
 
     MachineOpCode mopCode = MI->getOpcode();
-    latency = Target.getInstrInfo().hasResultInterlock(mopCode)
-      ? Target.getInstrInfo().minLatency(mopCode)
-      : Target.getInstrInfo().maxLatency(mopCode);
+    latency = Target.getInstrInfo()->hasResultInterlock(mopCode)
+      ? Target.getInstrInfo()->minLatency(mopCode)
+      : Target.getInstrInfo()->maxLatency(mopCode);
   }
 }
 
@@ -138,7 +138,7 @@
 
 void SchedGraph::addCDEdges(const TerminatorInst* term,
 			    const TargetMachine& target) {
-  const TargetInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = *target.getInstrInfo();
   MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
   
   // Find the first branch instr in the sequence of machine instrs for term
@@ -240,7 +240,7 @@
 // 
 void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
 			     const TargetMachine& target) {
-  const TargetInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = *target.getInstrInfo();
   
   // Instructions in memNodeVec are in execution order within the basic block,
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@ -272,7 +272,7 @@
 // 
 void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
 				 const TargetMachine& target) {
-  const TargetInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = *target.getInstrInfo();
   
   // Instructions in memNodeVec are in execution order within the basic block,
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@ -471,7 +471,7 @@
 				       std::vector<SchedGraphNode*>& callDepNodeVec,
 				       RegToRefVecMap& regToRefVecMap,
 				       ValueToDefVecMap& valueToDefVecMap) {
-  const TargetInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = *target.getInstrInfo();
   
   MachineOpCode opCode = node->getOpcode();
   
@@ -493,7 +493,7 @@
       unsigned regNum = mop.getReg();
       
       // If this is not a dummy zero register, record the reference in order
-      if (regNum != target.getRegInfo().getZeroRegNum())
+      if (regNum != target.getRegInfo()->getZeroRegNum())
         regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i));
 
@@ -502,8 +502,8 @@
       if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
         {
           unsigned rcid;
-          int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
-          if (target.getRegInfo().getMachineRegClass(rcid)
+          int regInClass = target.getRegInfo()->getClassRegNum(regNum, rcid);
+          if (target.getRegInfo()->getMachineRegClass(rcid)
               ->isRegVolatile(regInClass))
             callDepNodeVec.push_back(node);
         }
@@ -532,7 +532,7 @@
     const MachineOperand& mop = MI.getImplicitOp(i);
     if (mop.hasAllocatedReg()) {
       unsigned regNum = mop.getReg();
-      if (regNum != target.getRegInfo().getZeroRegNum())
+      if (regNum != target.getRegInfo()->getZeroRegNum())
         regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i + MI.getNumOperands()));
       continue;                     // nothing more to do
@@ -553,7 +553,7 @@
 				 std::vector<SchedGraphNode*>& callDepNodeVec,
 				 RegToRefVecMap& regToRefVecMap,
 				 ValueToDefVecMap& valueToDefVecMap) {
-  const TargetInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = *target.getInstrInfo();
   
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.