[llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp InstrSelectionSupport.cpp
Chris Lattner
lattner at cs.uiuc.edu
Wed Jun 2 01:03:01 PDT 2004
Changes in directory llvm/lib/Target/SparcV9/InstrSelection:
InstrSelection.cpp updated: 1.77 -> 1.78
InstrSelectionSupport.cpp updated: 1.67 -> 1.68
---
Log message:
Convert to the new TargetMachine interface.
---
Diffs of the changes: (+9 -9)
Index: llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
diff -u llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.77 llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.78
--- llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.77 Sat May 29 22:33:49 2004
+++ llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp Wed Jun 2 00:54:48 2004
@@ -220,8 +220,8 @@
MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN);
for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) {
std::vector<MachineInstr*> mvec, CpVec;
- Target.getRegInfo().cpValue2Value(PN->getIncomingValue(i), PhiCpRes,
- mvec);
+ Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
+ PhiCpRes, mvec);
for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
MI != mvec.end(); ++MI) {
std::vector<MachineInstr*> CpVec2 =
@@ -235,7 +235,7 @@
}
// Insert a copy instruction from PhiCpRes to PN.
std::vector<MachineInstr*> mvec;
- Target.getRegInfo().cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN),
+ Target.getRegInfo()->cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN),
mvec);
BB->insert(BB->begin(), mvec.begin(), mvec.end());
MCforPN.insert (MCforPN.end (), mvec.begin (), mvec.end ());
Index: llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
diff -u llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.67 llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.68
--- llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.67 Fri Apr 23 13:15:47 2004
+++ llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp Wed Jun 2 00:54:49 2004
@@ -40,7 +40,7 @@
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
- target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
+ target.getInstrInfo()->CreateCodeToLoadConst(target, F, opValue, tmpReg,
loadConstVec, mcfi);
// Record the mapping from the tmp VM instruction to machine instruction.
@@ -66,14 +66,14 @@
getImmedValue = 0;
if (canUseImmed &&
- target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) {
+ target.getInstrInfo()->constantFitsInImmedField(opCode, intValue)) {
opType = isSigned? MachineOperand::MO_SignExtendedImmed
: MachineOperand::MO_UnextendedImmed;
getImmedValue = intValue;
} else if (intValue == 0 &&
- target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
+ target.getRegInfo()->getZeroRegNum() != (unsigned)-1) {
opType = MachineOperand::MO_MachineRegister;
- getMachineRegNum = target.getRegInfo().getZeroRegNum();
+ getMachineRegNum = target.getRegInfo()->getZeroRegNum();
}
return opType;
@@ -95,7 +95,7 @@
// TargetInstrInfo::ConvertConstantToIntType() does the right conversions:
bool isValidConstant;
uint64_t valueToUse =
- target.getInstrInfo().ConvertConstantToIntType(target, val, val->getType(),
+ target.getInstrInfo()->ConvertConstantToIntType(target, val, val->getType(),
isValidConstant);
if (! isValidConstant)
return MachineOperand::MO_VirtualRegister;
@@ -130,7 +130,7 @@
std::vector<MachineInstr*> MVec;
MachineOpCode opCode = minstr->getOpcode();
- const TargetInstrInfo& instrInfo = target.getInstrInfo();
+ const TargetInstrInfo& instrInfo = *target.getInstrInfo();
int resultPos = instrInfo.getResultPos(opCode);
int immedPos = instrInfo.getImmedConstantPos(opCode);
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