[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp SparcV9CodeEmitter.cpp SparcV9FrameInfo.h SparcV9InstrInfo.cpp SparcV9InstrSelection.cpp SparcV9PeepholeOpts.cpp SparcV9PreSelection.cpp SparcV9PrologEpilogInserter.cpp SparcV9RegInfo.cpp SparcV9TargetMachine.h
Chris Lattner
lattner at cs.uiuc.edu
Wed Jun 2 01:00:06 PDT 2004
Changes in directory llvm/lib/Target/SparcV9:
SparcV9AsmPrinter.cpp updated: 1.113 -> 1.114
SparcV9CodeEmitter.cpp updated: 1.62 -> 1.63
SparcV9FrameInfo.h updated: 1.4 -> 1.5
SparcV9InstrInfo.cpp updated: 1.64 -> 1.65
SparcV9InstrSelection.cpp updated: 1.141 -> 1.142
SparcV9PeepholeOpts.cpp updated: 1.23 -> 1.24
SparcV9PreSelection.cpp updated: 1.33 -> 1.34
SparcV9PrologEpilogInserter.cpp updated: 1.38 -> 1.39
SparcV9RegInfo.cpp updated: 1.126 -> 1.127
SparcV9TargetMachine.h updated: 1.8 -> 1.9
---
Log message:
Convert to the new TargetMachine interface.
---
Diffs of the changes: (+115 -106)
Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.113 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.114
--- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.113 Tue May 25 03:50:52 2004
+++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Wed Jun 2 00:54:42 2004
@@ -74,6 +74,15 @@
arrayType->getElementType() == Type::SByteTy);
}
+ unsigned findOptimalStorageSize(const TargetMachine &TM, const Type *Ty) {
+ // All integer types smaller than ints promote to 4 byte integers.
+ if (Ty->isIntegral() && Ty->getPrimitiveSize() < 4)
+ return 4;
+
+ return TM.getTargetData().getTypeSize(Ty);
+ }
+
+
inline const std::string
TypeToDataDirective(const Type* type) {
switch(type->getPrimitiveID())
@@ -111,7 +120,7 @@
return 1 + CVA->getNumOperands();
}
- return target.findOptimalStorageSize(CV->getType());
+ return findOptimalStorageSize(target, CV->getType());
}
/// Align data larger than one L1 cache line on L1 cache line boundaries.
@@ -132,7 +141,7 @@
///
inline unsigned int
TypeToAlignment(const Type* type, const TargetMachine& target) {
- return SizeToAlignment(target.findOptimalStorageSize(type), target);
+ return SizeToAlignment(findOptimalStorageSize(target, type), target);
}
/// Get the size of the constant and then use SizeToAlignment.
@@ -580,9 +589,9 @@
inline bool
SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
unsigned int opNum) {
- if (Target.getInstrInfo().isLoad(MI->getOpcode()))
+ if (Target.getInstrInfo()->isLoad(MI->getOpcode()))
return (opNum == 0);
- else if (Target.getInstrInfo().isStore(MI->getOpcode()))
+ else if (Target.getInstrInfo()->isStore(MI->getOpcode()))
return (opNum == 1);
else
return false;
@@ -639,11 +648,11 @@
{
int regNum = (int)mop.getReg();
- if (regNum == Target.getRegInfo().getInvalidRegNum()) {
+ if (regNum == Target.getRegInfo()->getInvalidRegNum()) {
// better to print code with NULL registers than to die
toAsm << "<NULL VALUE>";
} else {
- toAsm << "%" << Target.getRegInfo().getUnifiedRegName(regNum);
+ toAsm << "%" << Target.getRegInfo()->getUnifiedRegName(regNum);
}
break;
}
@@ -693,10 +702,10 @@
void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
unsigned Opcode = MI->getOpcode();
- if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
+ if (Target.getInstrInfo()->isDummyPhiInstr(Opcode))
return; // IGNORE PHI NODES
- toAsm << "\t" << Target.getInstrInfo().getName(Opcode) << "\t";
+ toAsm << "\t" << Target.getInstrInfo()->getName(Opcode) << "\t";
unsigned Mask = getOperandMask(Opcode);
@@ -770,7 +779,7 @@
Target) << "\n";
toAsm << "\t.type\t" << getID(GV) << ",#object\n";
toAsm << "\t.reserve\t" << getID(GV) << ","
- << Target.findOptimalStorageSize(GV->getType()->getElementType())
+ << findOptimalStorageSize(Target, GV->getType()->getElementType())
<< "\n";
}
}
Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.62 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.63
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.62 Thu May 20 02:43:40 2004
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Wed Jun 2 00:54:42 2004
@@ -474,7 +474,7 @@
unsigned
SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
MachineInstr &MI) {
- const TargetRegInfo &RI = TM.getRegInfo();
+ const TargetRegInfo &RI = *TM.getRegInfo();
unsigned regClass, regType = RI.getRegType(fakeReg);
// At least map fakeReg into its class
fakeReg = RI.getClassRegNum(fakeReg, regClass);
@@ -656,7 +656,7 @@
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
<< realRegByClass << " (LLC: "
- << TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n");
+ << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
rv = realRegByClass;
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.4 llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.5
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.4 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.h Wed Jun 2 00:54:42 2004
@@ -72,22 +72,22 @@
// (generally FP or SP)
//
virtual int getIncomingArgBaseRegNum() const {
- return (int) target.getRegInfo().getFramePointer();
+ return (int) target.getRegInfo()->getFramePointer();
}
virtual int getOutgoingArgBaseRegNum() const {
- return (int) target.getRegInfo().getStackPointer();
+ return (int) target.getRegInfo()->getStackPointer();
}
virtual int getOptionalOutgoingArgBaseRegNum() const {
- return (int) target.getRegInfo().getStackPointer();
+ return (int) target.getRegInfo()->getStackPointer();
}
virtual int getAutomaticVarBaseRegNum() const {
- return (int) target.getRegInfo().getFramePointer();
+ return (int) target.getRegInfo()->getFramePointer();
}
virtual int getRegSpillAreaBaseRegNum() const {
- return (int) target.getRegInfo().getFramePointer();
+ return (int) target.getRegInfo()->getFramePointer();
}
virtual int getDynamicAreaBaseRegNum() const {
- return (int) target.getRegInfo().getStackPointer();
+ return (int) target.getRegInfo()->getStackPointer();
}
virtual int getIncomingArgOffset(MachineFunction& mcInfo,
Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.64 llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.65
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.64 Sun May 30 02:34:01 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp Wed Jun 2 00:54:42 2004
@@ -174,8 +174,7 @@
} else {
// unsigned or small signed value that fits in simm13 field of OR
assert(smallNegValue || (C & ~MAXSIMM) == 0);
- miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
- .getZeroRegNum())
+ miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()->getZeroRegNum())
.addSImm(sC).addRegDef(dest);
}
mvec.push_back(miOR);
@@ -588,7 +587,7 @@
mvec, mcfi);
}
- unsigned FPReg = target.getRegInfo().getFramePointer();
+ unsigned FPReg = target.getRegInfo()->getFramePointer();
unsigned StoreOpcode = ChooseStoreInstruction(storeType);
StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
mvec.push_back(BuildMI(StoreOpcode, 3)
@@ -633,7 +632,7 @@
//
int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
- unsigned FPReg = target.getRegInfo().getFramePointer();
+ unsigned FPReg = target.getRegInfo()->getFramePointer();
// Store instruction stores `val' to [%fp+offset].
// The store opCode is based only the source value being copied.
@@ -699,8 +698,8 @@
if (loadConstantToReg) {
// `src' is constant and cannot fit in immed field for the ADD
// Insert instructions to "load" the constant into a register
- target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
- mvec, mcfi);
+ target.getInstrInfo()->CreateCodeToLoadConst(target, F, src, dest,
+ mvec, mcfi);
} else {
// Create a reg-to-reg copy instruction for the given type:
// -- For FP values, create a FMOVS or FMOVD instruction
Index: llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.141 llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.142
--- llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.141 Sun May 23 00:10:06 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp Wed Jun 2 00:54:43 2004
@@ -592,12 +592,12 @@
castDestType));
// Create the fpreg-to-intreg copy code
- target.getInstrInfo().CreateCodeToCopyFloatToInt(target, F, destForCast,
+ target.getInstrInfo()->CreateCodeToCopyFloatToInt(target, F, destForCast,
fpToIntCopyDest, mvec, mcfi);
// Create the uint64_t to uint32_t conversion, if needed
if (destI->getType() == Type::UIntTy)
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI,
/*numLowBits*/ 32, mvec, mcfi);
}
@@ -743,7 +743,7 @@
CreateIntNegInstruction(const TargetMachine& target,
Value* vreg)
{
- return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo().getZeroRegNum())
+ return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo()->getZeroRegNum())
.addReg(vreg).addRegDef(vreg);
}
@@ -793,7 +793,7 @@
if (shiftDest != destVal) {
// extend the sign-bit of the result into all upper bits of dest
assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateSignExtensionInstructions(target, F, shiftDest, destVal,
8*opSize, mvec, mcfi);
}
@@ -811,7 +811,7 @@
MachineCodeForInstruction& mcfi)
{
/* Use max. multiply cost, viz., cost of MULX */
- unsigned cost = target.getInstrInfo().minLatency(V9::MULXr);
+ unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr);
unsigned firstNewInstr = mvec.size();
Value* constOp = rval;
@@ -826,7 +826,7 @@
if (resultType->isInteger() || isa<PointerType>(resultType)) {
bool isValidConst;
- int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target,
+ int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target,
constOp, constOp->getType(), isValidConst);
if (isValidConst) {
unsigned pow;
@@ -837,8 +837,8 @@
}
if (C == 0 || C == 1) {
- cost = target.getInstrInfo().minLatency(V9::ADDr);
- unsigned Zero = target.getRegInfo().getZeroRegNum();
+ cost = target.getInstrInfo()->minLatency(V9::ADDr);
+ unsigned Zero = target.getRegInfo()->getZeroRegNum();
MachineInstr* M;
if (C == 0)
M =BuildMI(V9::ADDr,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
@@ -873,7 +873,7 @@
if (firstNewInstr < mvec.size()) {
cost = 0;
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
- cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode());
+ cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode());
}
return cost;
@@ -897,7 +897,7 @@
Constant* P = ConstantExpr::get(Instruction::Mul,
cast<Constant>(lval),
cast<Constant>(rval));
- target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
+ target.getInstrInfo()->CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
}
else if (isa<Constant>(rval)) // rval is constant, but not lval
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
@@ -969,7 +969,7 @@
return;
Instruction* destVal = instrNode->getInstruction();
- unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
+ unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
// Cases worth optimizing are:
// (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
@@ -980,7 +980,7 @@
if (resultType->isInteger()) {
unsigned pow;
bool isValidConst;
- int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target,
+ int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target,
constOp, constOp->getType(), isValidConst);
if (isValidConst) {
bool needNeg = false;
@@ -1089,13 +1089,13 @@
// compile time if the total size is a known constant.
if (isa<Constant>(numElementsVal)) {
bool isValid;
- int64_t numElem = (int64_t) target.getInstrInfo().
+ int64_t numElem = (int64_t) target.getInstrInfo()->
ConvertConstantToIntType(target, numElementsVal,
numElementsVal->getType(), isValid);
assert(isValid && "Unexpectedly large array dimension in alloca!");
int64_t total = numElem * tsize;
- if (int extra= total % target.getFrameInfo().getStackFrameSizeAlignment())
- total += target.getFrameInfo().getStackFrameSizeAlignment() - extra;
+ if (int extra= total % target.getFrameInfo()->getStackFrameSizeAlignment())
+ total += target.getFrameInfo()->getStackFrameSizeAlignment() - extra;
totalSizeVal = ConstantSInt::get(Type::IntTy, total);
} else {
// The size is not a constant. Generate code to compute it and
@@ -1133,10 +1133,10 @@
bool growUp;
ConstantSInt* dynamicAreaOffset =
ConstantSInt::get(Type::IntTy,
- target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
+ target.getFrameInfo()->getDynamicAreaOffset(mcInfo,growUp));
assert(! growUp && "Has SPARC v9 stack frame convention changed?");
- unsigned SPReg = target.getRegInfo().getStackPointer();
+ unsigned SPReg = target.getRegInfo()->getStackPointer();
// Instruction 2: sub %sp, totalSizeVal -> %sp
getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
@@ -1180,8 +1180,8 @@
paddedSize,
tsize * numElements);
- if (((int)paddedSize) > 8 * target.getFrameInfo().getSizeOfEachArgOnStack() ||
- ! target.getInstrInfo().constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
+ if (((int)paddedSize) > 8 * target.getFrameInfo()->getSizeOfEachArgOnStack() ||
+ ! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
CreateCodeForVariableSizeAlloca(target, result, tsize,
ConstantSInt::get(Type::IntTy,numElements),
getMvec);
@@ -1196,7 +1196,7 @@
ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
// Instruction 1: add %fp, offsetFromFP -> result
- unsigned FPReg = target.getRegInfo().getFramePointer();
+ unsigned FPReg = target.getRegInfo()->getFramePointer();
getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal)
.addRegDef(result));
}
@@ -1408,9 +1408,9 @@
bool ignore;
Function* func = cast<Function>(callInstr.getParent()->getParent());
int numFixedArgs = func->getFunctionType()->getNumParams();
- int fpReg = target.getFrameInfo().getIncomingArgBaseRegNum();
- int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
- int firstVarArgOff = numFixedArgs * argSize + target.getFrameInfo().
+ int fpReg = target.getFrameInfo()->getIncomingArgBaseRegNum();
+ int argSize = target.getFrameInfo()->getSizeOfEachArgOnStack();
+ int firstVarArgOff = numFixedArgs * argSize + target.getFrameInfo()->
getFirstIncomingArgOffset(MachineFunction::get(func), ignore);
mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).
addRegDef(&callInstr));
@@ -1423,7 +1423,7 @@
case Intrinsic::vacopy:
// Simple copy of current va_list (arg1) to new va_list (result)
mvec.push_back(BuildMI(V9::ORr, 3).
- addMReg(target.getRegInfo().getZeroRegNum()).
+ addMReg(target.getRegInfo()->getZeroRegNum()).
addReg(callInstr.getOperand(1)).
addRegDef(&callInstr));
return true;
@@ -1539,7 +1539,7 @@
MachineInstr* retMI =
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
- .addMReg(target.getRegInfo().getZeroRegNum(), MachineOperand::Def);
+ .addMReg(target.getRegInfo()->getZeroRegNum(), MachineOperand::Def);
// If there is a value to return, we need to:
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
@@ -1549,7 +1549,7 @@
//
if (retVal != NULL) {
const SparcV9RegInfo& regInfo =
- (SparcV9RegInfo&) target.getRegInfo();
+ (SparcV9RegInfo&) *target.getRegInfo();
const Type* retType = retVal->getType();
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
unsigned retRegNum = (retType->isFloatingPoint()
@@ -1567,7 +1567,7 @@
retValToUse = new TmpInstruction(mcfi, retVal);
// sign-extend retVal and put the result in the temporary reg.
- target.getInstrInfo().CreateSignExtensionInstructions
+ target.getInstrInfo()->CreateSignExtensionInstructions
(target, returnInstr->getParent()->getParent(),
retVal, retValToUse, 8*retSize, mvec, mcfi);
}
@@ -1637,7 +1637,7 @@
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
- && target.getInstrInfo().ConvertConstantToIntType(target,
+ && target.getInstrInfo()->ConvertConstantToIntType(target,
constVal, constVal->getType(), isValidConst) == 0
&& isValidConst)
{
@@ -1747,7 +1747,7 @@
Instruction* notI = subtreeRoot->getInstruction();
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(subtreeRoot->getInstruction()));
- unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
+ unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
// Unconditionally set register to 0
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(notI));
@@ -1765,7 +1765,7 @@
{ // First find the unary operand. It may be left or right, usually right.
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(subtreeRoot->getInstruction()));
- unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
+ unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(notArg).addMReg(ZeroReg)
.addRegDef(subtreeRoot->getValue()));
break;
@@ -1889,15 +1889,15 @@
? new TmpInstruction(mcfi, destType, opVal)
: destI);
- target.getInstrInfo().CreateSignExtensionInstructions
+ target.getInstrInfo()->CreateSignExtensionInstructions
(target, currentFunc,opVal,signExtDest,extSourceInBits,mvec,mcfi);
if (signAndZeroExtend)
- target.getInstrInfo().CreateZeroExtensionInstructions
+ target.getInstrInfo()->CreateZeroExtensionInstructions
(target, currentFunc, signExtDest, destI, 8*destSize, mvec, mcfi);
}
else if (zeroExtendOnly) {
- target.getInstrInfo().CreateZeroExtensionInstructions
+ target.getInstrInfo()->CreateZeroExtensionInstructions
(target, currentFunc, opVal, destI, extSourceInBits, mvec, mcfi);
}
else
@@ -1955,7 +1955,7 @@
MachineCodeForInstruction::get(dest);
srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest);
- target.getInstrInfo().CreateCodeToCopyIntToFloat(target,
+ target.getInstrInfo()->CreateCodeToCopyIntToFloat(target,
dest->getParent()->getParent(),
leftVal, cast<Instruction>(srcForCast),
mvec, destMCFI);
@@ -2067,12 +2067,12 @@
MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(divI);
divOp1ToUse = new TmpInstruction(mcfi, divOp1);
divOp2ToUse = new TmpInstruction(mcfi, divOp2);
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateSignExtensionInstructions(target,
divI->getParent()->getParent(),
divOp1, divOp1ToUse,
8*opSize, mvec, mcfi);
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateSignExtensionInstructions(target,
divI->getParent()->getParent(),
divOp2, divOp2ToUse,
@@ -2109,7 +2109,7 @@
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
if (opSize < 8) {
divOpToUse = new TmpInstruction(mcfi, divOp2);
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateSignExtensionInstructions(target,
remI->getParent()->getParent(),
divOp2, divOpToUse,
@@ -2251,7 +2251,7 @@
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
- && target.getInstrInfo().ConvertConstantToIntType(target,
+ && target.getInstrInfo()->ConvertConstantToIntType(target,
constVal, constVal->getType(), isValidConst) == 0
&& isValidConst)
{
@@ -2328,10 +2328,10 @@
rightOpToUse = new TmpInstruction(mcfi, rightVal);
// sign-extend each operand and put the result in the temporary reg.
- target.getInstrInfo().CreateSignExtensionInstructions
+ target.getInstrInfo()->CreateSignExtensionInstructions
(target, setCCInstr->getParent()->getParent(),
leftVal, leftOpToUse, 8*opSize, mvec, mcfi);
- target.getInstrInfo().CreateSignExtensionInstructions
+ target.getInstrInfo()->CreateSignExtensionInstructions
(target, setCCInstr->getParent()->getParent(),
rightVal, rightOpToUse, 8*opSize, mvec, mcfi);
}
@@ -2342,8 +2342,8 @@
mvec.push_back(BuildMI(V9::SUBccr, 4)
.addReg(leftOpToUse)
.addReg(rightOpToUse)
- .addMReg(target.getRegInfo()
- .getZeroRegNum(), MachineOperand::Def)
+ .addMReg(target.getRegInfo()->
+ getZeroRegNum(), MachineOperand::Def)
.addCCReg(tmpForCC, MachineOperand::Def));
} else {
// FP condition: dest of FCMP should be some FCCn register
@@ -2456,8 +2456,8 @@
MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(callInstr);
const SparcV9RegInfo& regInfo =
- (SparcV9RegInfo&) target.getRegInfo();
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ (SparcV9RegInfo&) *target.getRegInfo();
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
// Create hidden virtual register for return address with type void*
TmpInstruction* retAddrReg =
@@ -2506,7 +2506,7 @@
TmpInstruction* argExtend = new TmpInstruction(mcfi, argVal);
// sign-extend argVal and put the result in the temporary reg.
- target.getInstrInfo().CreateSignExtensionInstructions
+ target.getInstrInfo()->CreateSignExtensionInstructions
(target, currentFunc, argVal, argExtend,
8*argSize, mvec, mcfi);
@@ -2787,7 +2787,7 @@
Instruction* vaNextI = subtreeRoot->getInstruction();
assert(target.getTargetData().getTypeSize(vaNextI->getType()) <= 8 &&
"We assumed that all LLVM parameter types <= 8 bytes!");
- int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
+ int argSize = target.getFrameInfo()->getSizeOfEachArgOnStack();
mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaNextI->getOperand(0)).
addSImm(argSize).addRegDef(vaNextI));
break;
@@ -2826,7 +2826,7 @@
else {
std::vector<MachineInstr*> minstrVec;
Instruction* instr = subtreeRoot->getInstruction();
- target.getInstrInfo().
+ target.getInstrInfo()->
CreateCopyInstructionsByType(target,
instr->getParent()->getParent(),
instr->getOperand(forwardOperandNum),
Index: llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.23 llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.24
--- llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.23 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp Wed Jun 2 00:54:43 2004
@@ -31,7 +31,7 @@
const TargetMachine& target) {
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin()) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
MachineBasicBlock::iterator predMI = prior(BBI);
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
// This instruction is in a delay slot of its predecessor, so
@@ -83,7 +83,7 @@
return (// either operand otherOp is register %g0
(MI->getOperand(otherOp).hasAllocatedReg() &&
MI->getOperand(otherOp).getReg() ==
- target.getRegInfo().getZeroRegNum()) ||
+ target.getRegInfo()->getZeroRegNum()) ||
// or operand otherOp == 0
(MI->getOperand(otherOp).getType()
Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.33 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.34
--- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.33 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Wed Jun 2 00:54:43 2004
@@ -41,7 +41,7 @@
public:
PreSelection(const TargetMachine &T)
- : instrInfo(T.getInstrInfo()) {}
+ : instrInfo(*T.getInstrInfo()) {}
// runOnFunction - apply this pass to each Function
bool runOnFunction(Function &F) {
Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.38 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.39
--- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.38 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Wed Jun 2 00:54:43 2004
@@ -52,7 +52,7 @@
//------------------------------------------------------------------------
static unsigned getStaticStackSize (MachineFunction &MF) {
- const TargetFrameInfo& frameInfo = MF.getTarget().getFrameInfo();
+ const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo();
unsigned staticStackSize = MF.getInfo()->getStaticStackSize();
@@ -69,7 +69,7 @@
{
std::vector<MachineInstr*> mvec;
const TargetMachine &TM = MF.getTarget();
- const TargetFrameInfo& frameInfo = TM.getFrameInfo();
+ const TargetFrameInfo& frameInfo = *TM.getFrameInfo();
// The second operand is the stack size. If it does not fit in the
// immediate field, we have to use a free register to hold the size.
@@ -77,8 +77,8 @@
//
unsigned staticStackSize = getStaticStackSize (MF);
int32_t C = - (int) staticStackSize;
- int SP = TM.getRegInfo().getStackPointer();
- if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
+ int SP = TM.getRegInfo()->getStackPointer();
+ if (TM.getInstrInfo()->constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
.addMReg(SP, MachineOperand::Def));
} else {
@@ -87,8 +87,8 @@
// local (%l) and in (%i) registers cannot be used before the SAVE!
// Do this by creating a code sequence equivalent to:
// SETSW -(stackSize), %g1
- int uregNum = TM.getRegInfo().getUnifiedRegNum(
- TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
+ int uregNum = TM.getRegInfo()->getUnifiedRegNum(
+ TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
SparcV9IntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
@@ -120,15 +120,16 @@
//
if (MF.getFunction()->getFunctionType()->isVarArg()) {
int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
- int numArgRegs = TM.getRegInfo().getNumOfIntArgRegs();
+ int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs();
if (numFixedArgs < numArgRegs) {
+ const TargetFrameInfo &FI = *TM.getFrameInfo();
bool ignore;
- int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
- TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
+ int firstArgReg = TM.getRegInfo()->getUnifiedRegNum(
+ TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
SparcV9IntRegClass::i0);
- int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
- int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
- int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);
+ int fpReg = FI.getIncomingArgBaseRegNum();
+ int argSize = FI.getSizeOfEachArgOnStack();
+ int firstArgOffset= FI.getFirstIncomingArgOffset(MF,ignore);
int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
for (int i=numFixedArgs; i < numArgRegs; ++i) {
@@ -145,7 +146,7 @@
void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
const TargetMachine &TM = MF.getTarget();
- const TargetInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &MII = *TM.getInstrInfo();
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock &MBB = *I;
@@ -153,7 +154,7 @@
const Instruction *TermInst = (Instruction*)BB.getTerminator();
if (TermInst->getOpcode() == Instruction::Ret)
{
- int ZR = TM.getRegInfo().getZeroRegNum();
+ int ZR = TM.getRegInfo()->getZeroRegNum();
MachineInstr *Restore =
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
.addMReg(ZR, MachineOperand::Def);
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.126 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.127
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.126 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Jun 2 00:54:43 2004
@@ -314,7 +314,7 @@
void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
+ assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
@@ -482,7 +482,7 @@
// Now the arg is coming on stack. Since the LR received a register,
// we just have to load the arg on stack into that register
//
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
@@ -540,7 +540,7 @@
// since this method is called before any other method that makes
// uses of the stack pos of the LR (e.g., updateMachineInstr)
//
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
@@ -572,7 +572,7 @@
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
- assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
+ assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@@ -641,7 +641,7 @@
void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
+ assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
suggestReg4RetAddr(RetMI, LRI);
@@ -764,7 +764,7 @@
// Use the register allocator, PRA, to find an unused reg. at this MI.
//
if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
+ if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
@@ -779,21 +779,21 @@
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::STXi, Offset))
MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::STFi, Offset))
MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::STDFi, Offset))
MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
@@ -815,7 +815,7 @@
case FloatCCRegType: {
unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::STXFSRi, Offset))
MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
else
MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
@@ -850,7 +850,7 @@
// Use the register allocator, PRA, to find an unused reg. at this MI.
//
if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
+ if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
@@ -865,7 +865,7 @@
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset))
MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
@@ -874,7 +874,7 @@
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::LDFi, Offset))
MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
@@ -883,7 +883,7 @@
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::LDDFi, Offset))
MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
@@ -906,7 +906,7 @@
case FloatCCRegType: {
unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
+ if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXFSRi, Offset))
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(fsrRegNum, MachineOperand::UseAndDef);
else
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.h
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.8 llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.9
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.8 Sun Apr 25 02:04:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.h Wed Jun 2 00:54:43 2004
@@ -34,10 +34,10 @@
public:
SparcV9TargetMachine(IntrinsicLowering *IL);
- virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
- virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
- virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
- virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
+ virtual const TargetInstrInfo *getInstrInfo() const { return &instrInfo; }
+ virtual const TargetSchedInfo *getSchedInfo() const { return &schedInfo; }
+ virtual const TargetRegInfo *getRegInfo() const { return ®Info; }
+ virtual const TargetFrameInfo *getFrameInfo() const { return &frameInfo; }
virtual TargetJITInfo *getJITInfo() { return &jitInfo; }
virtual const MRegisterInfo *getRegisterInfo() const {
return &instrInfo.getRegisterInfo();
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