[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.248 -> 1.249

---
Log message:

Fix some comments, avoid sign extending booleans when zero extend works fine


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Diffs of the changes:  (+5 -5)

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.248 llvm/lib/Target/X86/InstSelectSimple.cpp:1.249
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.248	Sun May  9 17:28:45 2004
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Sun May  9 18:16:33 2004
@@ -886,9 +886,9 @@
         // each, then uses a conditional move to handle the overflow case.  For
         // example, a setlt for long would generate code like this:
         //
-        // AL = lo(op1) < lo(op2)   // Signedness depends on operands
-        // BL = hi(op1) < hi(op2)   // Always unsigned comparison
-        // dest = hi(op1) == hi(op2) ? AL : BL;
+        // AL = lo(op1) < lo(op2)   // Always unsigned comparison
+        // BL = hi(op1) < hi(op2)   // Signedness depends on operands
+        // dest = hi(op1) == hi(op2) ? BL : AL;
         //
 
         // FIXME: This would be much better if we had hierarchical register
@@ -960,7 +960,7 @@
       //
       // AL = lo(op1) < lo(op2)   // Signedness depends on operands
       // BL = hi(op1) < hi(op2)   // Always unsigned comparison
-      // dest = hi(op1) == hi(op2) ? AL : BL;
+      // dest = hi(op1) == hi(op2) ? BL : AL;
       //
 
       // FIXME: This would be much better if we had hierarchical register
@@ -1193,7 +1193,7 @@
 /// operand, in the specified target register.
 ///
 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
-  bool isUnsigned = VR.Ty->isUnsigned();
+  bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
 
   Value *Val = VR.Val;
   const Type *Ty = VR.Ty;