[llvm-commits] [parallel] CVS: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp InstSelectSimple.cpp SparcV8.h SparcV8InstrInfo.td SparcV8RegisterInfo.cpp SparcV8RegisterInfo.td SparcV8TargetMachine.cpp
Misha Brukman
brukman at cs.uiuc.edu
Wed Mar 10 19:05:10 PST 2004
Changes in directory llvm/lib/Target/SparcV8:
SparcV8AsmPrinter.cpp added (r1.3.2.1)
InstSelectSimple.cpp updated: 1.1.2.1 -> 1.1.2.2
SparcV8.h updated: 1.2.2.1 -> 1.2.2.2
SparcV8InstrInfo.td updated: 1.1.2.1 -> 1.1.2.2
SparcV8RegisterInfo.cpp updated: 1.3.2.1 -> 1.3.2.2
SparcV8RegisterInfo.td updated: 1.3.2.1 -> 1.3.2.2
SparcV8TargetMachine.cpp updated: 1.4.2.1 -> 1.4.2.2
---
Log message:
Merge from trunk.
---
Diffs of the changes: (+828 -38)
Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.3.2.1
*** /dev/null Wed Mar 10 19:03:59 2004
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp Wed Mar 10 19:03:49 2004
***************
*** 0 ****
--- 1,529 ----
+ //===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains a printer that converts from our internal representation
+ // of machine-dependent LLVM code to GAS-format Sparc V8 assembly language.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8.h"
+ #include "SparcV8InstrInfo.h"
+ #include "llvm/Constants.h"
+ #include "llvm/DerivedTypes.h"
+ #include "llvm/Module.h"
+ #include "llvm/Assembly/Writer.h"
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/CodeGen/MachineConstantPool.h"
+ #include "llvm/CodeGen/MachineInstr.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Support/Mangler.h"
+ #include "Support/Statistic.h"
+ #include "Support/StringExtras.h"
+ #include "Support/CommandLine.h"
+ #include <cctype>
+ using namespace llvm;
+
+ namespace {
+ Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
+
+ struct V8Printer : public MachineFunctionPass {
+ /// Output stream on which we're printing assembly code.
+ ///
+ std::ostream &O;
+
+ /// Target machine description which we query for reg. names, data
+ /// layout, etc.
+ ///
+ TargetMachine &TM;
+
+ /// Name-mangler for global names.
+ ///
+ Mangler *Mang;
+
+ V8Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { }
+
+ /// We name each basic block in a Function with a unique number, so
+ /// that we can consistently refer to them later. This is cleared
+ /// at the beginning of each call to runOnMachineFunction().
+ ///
+ typedef std::map<const Value *, unsigned> ValueMapTy;
+ ValueMapTy NumberForBB;
+
+ /// Cache of mangled name for current function. This is
+ /// recalculated at the beginning of each call to
+ /// runOnMachineFunction().
+ ///
+ std::string CurrentFnName;
+
+ virtual const char *getPassName() const {
+ return "SparcV8 Assembly Printer";
+ }
+
+ void emitConstantValueOnly(const Constant *CV);
+ void emitGlobalConstant(const Constant *CV);
+ void printConstantPool(MachineConstantPool *MCP);
+ void printOperand(const MachineOperand &MI);
+ void printMachineInstruction(const MachineInstr *MI);
+ bool runOnMachineFunction(MachineFunction &F);
+ bool doInitialization(Module &M);
+ bool doFinalization(Module &M);
+ };
+ } // end of anonymous namespace
+
+ /// createSparcV8CodePrinterPass - Returns a pass that prints the SparcV8
+ /// assembly code for a MachineFunction to the given output stream,
+ /// using the given target machine description. This should work
+ /// regardless of whether the function is in SSA form.
+ ///
+ FunctionPass *llvm::createSparcV8CodePrinterPass (std::ostream &o,
+ TargetMachine &tm) {
+ return new V8Printer(o, tm);
+ }
+
+ /// toOctal - Convert the low order bits of X into an octal digit.
+ ///
+ static inline char toOctal(int X) {
+ return (X&7)+'0';
+ }
+
+ /// getAsCString - Return the specified array as a C compatible
+ /// string, only if the predicate isStringCompatible is true.
+ ///
+ static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
+ assert(CVA->isString() && "Array is not string compatible!");
+
+ O << "\"";
+ for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
+ unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
+
+ if (C == '"') {
+ O << "\\\"";
+ } else if (C == '\\') {
+ O << "\\\\";
+ } else if (isprint(C)) {
+ O << C;
+ } else {
+ switch(C) {
+ case '\b': O << "\\b"; break;
+ case '\f': O << "\\f"; break;
+ case '\n': O << "\\n"; break;
+ case '\r': O << "\\r"; break;
+ case '\t': O << "\\t"; break;
+ default:
+ O << '\\';
+ O << toOctal(C >> 6);
+ O << toOctal(C >> 3);
+ O << toOctal(C >> 0);
+ break;
+ }
+ }
+ }
+ O << "\"";
+ }
+
+ // Print out the specified constant, without a storage class. Only the
+ // constants valid in constant expressions can occur here.
+ void V8Printer::emitConstantValueOnly(const Constant *CV) {
+ if (CV->isNullValue())
+ O << "0";
+ else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
+ assert(CB == ConstantBool::True);
+ O << "1";
+ } else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV))
+ if (((CI->getValue() << 32) >> 32) == CI->getValue())
+ O << CI->getValue();
+ else
+ O << (unsigned long long)CI->getValue();
+ else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV))
+ O << CI->getValue();
+ else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV))
+ // This is a constant address for a global variable or function. Use the
+ // name of the variable or function as the address value.
+ O << Mang->getValueName(CPR->getValue());
+ else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
+ const TargetData &TD = TM.getTargetData();
+ switch(CE->getOpcode()) {
+ case Instruction::GetElementPtr: {
+ // generate a symbolic expression for the byte address
+ const Constant *ptrVal = CE->getOperand(0);
+ std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end());
+ if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) {
+ O << "(";
+ emitConstantValueOnly(ptrVal);
+ O << ") + " << Offset;
+ } else {
+ emitConstantValueOnly(ptrVal);
+ }
+ break;
+ }
+ case Instruction::Cast: {
+ // Support only non-converting or widening casts for now, that is, ones
+ // that do not involve a change in value. This assertion is really gross,
+ // and may not even be a complete check.
+ Constant *Op = CE->getOperand(0);
+ const Type *OpTy = Op->getType(), *Ty = CE->getType();
+
+ // Pointers on ILP32 machines can be losslessly converted back and
+ // forth into 32-bit or wider integers, regardless of signedness.
+ assert(((isa<PointerType>(OpTy)
+ && (Ty == Type::LongTy || Ty == Type::ULongTy
+ || Ty == Type::IntTy || Ty == Type::UIntTy))
+ || (isa<PointerType>(Ty)
+ && (OpTy == Type::LongTy || OpTy == Type::ULongTy
+ || OpTy == Type::IntTy || OpTy == Type::UIntTy))
+ || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy))
+ && OpTy->isLosslesslyConvertibleTo(Ty))))
+ && "FIXME: Don't yet support this kind of constant cast expr");
+ O << "(";
+ emitConstantValueOnly(Op);
+ O << ")";
+ break;
+ }
+ case Instruction::Add:
+ O << "(";
+ emitConstantValueOnly(CE->getOperand(0));
+ O << ") + (";
+ emitConstantValueOnly(CE->getOperand(1));
+ O << ")";
+ break;
+ default:
+ assert(0 && "Unsupported operator!");
+ }
+ } else {
+ assert(0 && "Unknown constant value!");
+ }
+ }
+
+ // Print a constant value or values, with the appropriate storage class as a
+ // prefix.
+ void V8Printer::emitGlobalConstant(const Constant *CV) {
+ const TargetData &TD = TM.getTargetData();
+
+ if (CV->isNullValue()) {
+ O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n";
+ return;
+ } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
+ if (CVA->isString()) {
+ O << "\t.ascii\t";
+ printAsCString(O, CVA);
+ O << "\n";
+ } else { // Not a string. Print the values in successive locations
+ const std::vector<Use> &constValues = CVA->getValues();
+ for (unsigned i=0; i < constValues.size(); i++)
+ emitGlobalConstant(cast<Constant>(constValues[i].get()));
+ }
+ return;
+ } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
+ // Print the fields in successive locations. Pad to align if needed!
+ const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType());
+ const std::vector<Use>& constValues = CVS->getValues();
+ unsigned sizeSoFar = 0;
+ for (unsigned i=0, N = constValues.size(); i < N; i++) {
+ const Constant* field = cast<Constant>(constValues[i].get());
+
+ // Check if padding is needed and insert one or more 0s.
+ unsigned fieldSize = TD.getTypeSize(field->getType());
+ unsigned padSize = ((i == N-1? cvsLayout->StructSize
+ : cvsLayout->MemberOffsets[i+1])
+ - cvsLayout->MemberOffsets[i]) - fieldSize;
+ sizeSoFar += fieldSize + padSize;
+
+ // Now print the actual field value
+ emitGlobalConstant(field);
+
+ // Insert the field padding unless it's zero bytes...
+ if (padSize)
+ O << "\t.zero\t " << padSize << "\n";
+ }
+ assert(sizeSoFar == cvsLayout->StructSize &&
+ "Layout of constant struct may be incorrect!");
+ return;
+ } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
+ // FP Constants are printed as integer constants to avoid losing
+ // precision...
+ double Val = CFP->getValue();
+ switch (CFP->getType()->getPrimitiveID()) {
+ default: assert(0 && "Unknown floating point type!");
+ case Type::FloatTyID: {
+ union FU { // Abide by C TBAA rules
+ float FVal;
+ unsigned UVal;
+ } U;
+ U.FVal = Val;
+ O << ".long\t" << U.UVal << "\t# float " << Val << "\n";
+ return;
+ }
+ case Type::DoubleTyID: {
+ union DU { // Abide by C TBAA rules
+ double FVal;
+ uint64_t UVal;
+ } U;
+ U.FVal = Val;
+ O << ".quad\t" << U.UVal << "\t# double " << Val << "\n";
+ return;
+ }
+ }
+ }
+
+ const Type *type = CV->getType();
+ O << "\t";
+ switch (type->getPrimitiveID()) {
+ case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID:
+ O << ".byte";
+ break;
+ case Type::UShortTyID: case Type::ShortTyID:
+ O << ".word";
+ break;
+ case Type::FloatTyID: case Type::PointerTyID:
+ case Type::UIntTyID: case Type::IntTyID:
+ O << ".long";
+ break;
+ case Type::DoubleTyID:
+ case Type::ULongTyID: case Type::LongTyID:
+ O << ".quad";
+ break;
+ default:
+ assert (0 && "Can't handle printing this type of thing");
+ break;
+ }
+ O << "\t";
+ emitConstantValueOnly(CV);
+ O << "\n";
+ }
+
+ /// printConstantPool - Print to the current output stream assembly
+ /// representations of the constants in the constant pool MCP. This is
+ /// used to print out constants which have been "spilled to memory" by
+ /// the code generator.
+ ///
+ void V8Printer::printConstantPool(MachineConstantPool *MCP) {
+ const std::vector<Constant*> &CP = MCP->getConstants();
+ const TargetData &TD = TM.getTargetData();
+
+ if (CP.empty()) return;
+
+ for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+ O << "\t.section .rodata\n";
+ O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
+ << "\n";
+ O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
+ << *CP[i] << "\n";
+ emitGlobalConstant(CP[i]);
+ }
+ }
+
+ /// runOnMachineFunction - This uses the printMachineInstruction()
+ /// method to print assembly for each instruction.
+ ///
+ bool V8Printer::runOnMachineFunction(MachineFunction &MF) {
+ // BBNumber is used here so that a given Printer will never give two
+ // BBs the same name. (If you have a better way, please let me know!)
+ static unsigned BBNumber = 0;
+
+ O << "\n\n";
+ // What's my mangled name?
+ CurrentFnName = Mang->getValueName(MF.getFunction());
+
+ // Print out constants referenced by the function
+ printConstantPool(MF.getConstantPool());
+
+ // Print out labels for the function.
+ O << "\t.text\n";
+ O << "\t.align 16\n";
+ O << "\t.globl\t" << CurrentFnName << "\n";
+ O << "\t.type\t" << CurrentFnName << ", @function\n";
+ O << CurrentFnName << ":\n";
+
+ // Number each basic block so that we can consistently refer to them
+ // in PC-relative references.
+ NumberForBB.clear();
+ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+ I != E; ++I) {
+ NumberForBB[I->getBasicBlock()] = BBNumber++;
+ }
+
+ // Print out code for the function.
+ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+ I != E; ++I) {
+ // Print a label for the basic block.
+ O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# "
+ << I->getBasicBlock()->getName() << "\n";
+ for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
+ II != E; ++II) {
+ // Print the assembly for the instruction.
+ O << "\t";
+ printMachineInstruction(II);
+ }
+ }
+
+ // We didn't modify anything.
+ return false;
+ }
+
+
+ std::string LowercaseString (const std::string &S) {
+ std::string result (S);
+ for (unsigned i = 0; i < S.length(); ++i)
+ if (isupper (result[i]))
+ result[i] = tolower(result[i]);
+ return result;
+ }
+
+ void V8Printer::printOperand(const MachineOperand &MO) {
+ const MRegisterInfo &RI = *TM.getRegisterInfo();
+ switch (MO.getType()) {
+ case MachineOperand::MO_VirtualRegister:
+ if (Value *V = MO.getVRegValueOrNull()) {
+ O << "<" << V->getName() << ">";
+ return;
+ }
+ // FALLTHROUGH
+ case MachineOperand::MO_MachineRegister:
+ if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
+ else
+ O << "%reg" << MO.getReg();
+ return;
+
+ case MachineOperand::MO_SignExtendedImmed:
+ case MachineOperand::MO_UnextendedImmed:
+ O << (int)MO.getImmedValue();
+ return;
+ case MachineOperand::MO_PCRelativeDisp: {
+ ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
+ assert (i != NumberForBB.end()
+ && "Could not find a BB in the NumberForBB map!");
+ O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
+ return;
+ }
+ case MachineOperand::MO_GlobalAddress:
+ O << Mang->getValueName(MO.getGlobal());
+ return;
+ case MachineOperand::MO_ExternalSymbol:
+ O << MO.getSymbolName();
+ return;
+ default:
+ O << "<unknown operand type>"; return;
+ }
+ }
+
+ /// printMachineInstruction -- Print out a single SparcV8 LLVM instruction
+ /// MI in GAS syntax to the current output stream.
+ ///
+ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
+ unsigned Opcode = MI->getOpcode();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
+ const TargetInstrDescriptor &Desc = TII.get(Opcode);
+ O << Desc.Name << " ";
+
+ // print non-immediate, non-register-def operands
+ // then print immediate operands
+ // then print register-def operands.
+ std::vector<MachineOperand> print_order;
+ for (unsigned i = 0; i < MI->getNumOperands (); ++i)
+ if (!(MI->getOperand (i).isImmediate ()
+ || (MI->getOperand (i).isRegister ()
+ && MI->getOperand (i).isDef ())))
+ print_order.push_back (MI->getOperand (i));
+ for (unsigned i = 0; i < MI->getNumOperands (); ++i)
+ if (MI->getOperand (i).isImmediate ())
+ print_order.push_back (MI->getOperand (i));
+ for (unsigned i = 0; i < MI->getNumOperands (); ++i)
+ if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
+ print_order.push_back (MI->getOperand (i));
+ for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
+ printOperand (print_order[i]);
+ if (i != (print_order.size () - 1))
+ O << ", ";
+ }
+ O << "\n";
+ }
+
+ bool V8Printer::doInitialization(Module &M) {
+ Mang = new Mangler(M);
+ return false; // success
+ }
+
+ // SwitchSection - Switch to the specified section of the executable if we are
+ // not already in it!
+ //
+ static void SwitchSection(std::ostream &OS, std::string &CurSection,
+ const char *NewSection) {
+ if (CurSection != NewSection) {
+ CurSection = NewSection;
+ if (!CurSection.empty())
+ OS << "\t" << NewSection << "\n";
+ }
+ }
+
+ bool V8Printer::doFinalization(Module &M) {
+ const TargetData &TD = TM.getTargetData();
+ std::string CurSection;
+
+ // Print out module-level global variables here.
+ for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
+ if (I->hasInitializer()) { // External global require no code
+ O << "\n\n";
+ std::string name = Mang->getValueName(I);
+ Constant *C = I->getInitializer();
+ unsigned Size = TD.getTypeSize(C->getType());
+ unsigned Align = TD.getTypeAlignment(C->getType());
+
+ if (C->isNullValue() &&
+ (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
+ I->hasWeakLinkage() /* FIXME: Verify correct */)) {
+ SwitchSection(O, CurSection, ".data");
+ if (I->hasInternalLinkage())
+ O << "\t.local " << name << "\n";
+
+ O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
+ << "," << (unsigned)TD.getTypeAlignment(C->getType());
+ O << "\t\t# ";
+ WriteAsOperand(O, I, true, true, &M);
+ O << "\n";
+ } else {
+ switch (I->getLinkage()) {
+ case GlobalValue::LinkOnceLinkage:
+ case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
+ // Nonnull linkonce -> weak
+ O << "\t.weak " << name << "\n";
+ SwitchSection(O, CurSection, "");
+ O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n";
+ break;
+
+ case GlobalValue::AppendingLinkage:
+ // FIXME: appending linkage variables should go into a section of
+ // their name or something. For now, just emit them as external.
+ case GlobalValue::ExternalLinkage:
+ // If external or appending, declare as a global symbol
+ O << "\t.globl " << name << "\n";
+ // FALL THROUGH
+ case GlobalValue::InternalLinkage:
+ if (C->isNullValue())
+ SwitchSection(O, CurSection, ".bss");
+ else
+ SwitchSection(O, CurSection, ".data");
+ break;
+ }
+
+ O << "\t.align " << Align << "\n";
+ O << "\t.type " << name << ", at object\n";
+ O << "\t.size " << name << "," << Size << "\n";
+ O << name << ":\t\t\t\t# ";
+ WriteAsOperand(O, I, true, true, &M);
+ O << " = ";
+ WriteAsOperand(O, C, false, false, &M);
+ O << "\n";
+ emitGlobalConstant(C);
+ }
+ }
+
+ delete Mang;
+ return false; // success
+ }
Index: llvm/lib/Target/SparcV8/InstSelectSimple.cpp
diff -u llvm/lib/Target/SparcV8/InstSelectSimple.cpp:1.1.2.1 llvm/lib/Target/SparcV8/InstSelectSimple.cpp:1.1.2.2
--- llvm/lib/Target/SparcV8/InstSelectSimple.cpp:1.1.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/InstSelectSimple.cpp Wed Mar 10 19:03:49 2004
@@ -12,11 +12,14 @@
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
+#include "SparcV8InstrInfo.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicLowering.h"
#include "llvm/Pass.h"
+#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/InstVisitor.h"
@@ -54,6 +57,7 @@
BB = MBBMap[&LLVM_BB];
}
+ void visitBinaryOperator(BinaryOperator &I);
void visitReturnInst(ReturnInst &RI);
void visitInstruction(Instruction &I) {
@@ -65,9 +69,71 @@
/// function, lowering any calls to unknown intrinsic functions into the
/// equivalent LLVM code.
void LowerUnknownIntrinsicFunctionCalls(Function &F);
+ void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
+ /// copyConstantToRegister - Output the instructions required to put the
+ /// specified constant into the specified register.
+ ///
+ void copyConstantToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ Constant *C, unsigned R);
- void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
+ /// makeAnotherReg - This method returns the next register number we haven't
+ /// yet used.
+ ///
+ /// Long values are handled somewhat specially. They are always allocated
+ /// as pairs of 32 bit integer values. The register number returned is the
+ /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
+ /// of the long value.
+ ///
+ unsigned makeAnotherReg(const Type *Ty) {
+ assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
+ "Current target doesn't have SparcV8 reg info??");
+ const SparcV8RegisterInfo *MRI =
+ static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
+ if (Ty == Type::LongTy || Ty == Type::ULongTy) {
+ const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
+ // Create the lower part
+ F->getSSARegMap()->createVirtualRegister(RC);
+ // Create the upper part.
+ return F->getSSARegMap()->createVirtualRegister(RC)-1;
+ }
+
+ // Add the mapping of regnumber => reg class to MachineFunction
+ const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
+ return F->getSSARegMap()->createVirtualRegister(RC);
+ }
+
+ unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
+ unsigned getReg(Value *V) {
+ // Just append to the end of the current bb.
+ MachineBasicBlock::iterator It = BB->end();
+ return getReg(V, BB, It);
+ }
+ unsigned getReg(Value *V, MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IPt) {
+ unsigned &Reg = RegMap[V];
+ if (Reg == 0) {
+ Reg = makeAnotherReg(V->getType());
+ RegMap[V] = Reg;
+ }
+ // If this operand is a constant, emit the code to copy the constant into
+ // the register here...
+ //
+ if (Constant *C = dyn_cast<Constant>(V)) {
+ copyConstantToRegister(MBB, IPt, C, Reg);
+ RegMap.erase(V); // Assign a new name to this constant if ref'd again
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ // Move the address of the global into the register
+ unsigned TmpReg = makeAnotherReg(V->getType());
+ BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
+ BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
+ .addGlobalAddress (GV);
+ RegMap.erase(V); // Assign a new name to this address if ref'd again
+ }
+
+ return Reg;
+ }
};
}
@@ -76,6 +142,55 @@
return new V8ISel(TM);
}
+enum TypeClass {
+ cByte, cShort, cInt, cFloat, cDouble
+};
+
+static TypeClass getClass (const Type *T) {
+ switch (T->getPrimitiveID ()) {
+ case Type::UByteTyID: case Type::SByteTyID: return cByte;
+ case Type::UShortTyID: case Type::ShortTyID: return cShort;
+ case Type::UIntTyID: case Type::IntTyID: return cInt;
+ case Type::FloatTyID: return cFloat;
+ case Type::DoubleTyID: return cDouble;
+ default:
+ assert (0 && "Type of unknown class passed to getClass?");
+ return cByte;
+ }
+}
+
+/// copyConstantToRegister - Output the instructions required to put the
+/// specified constant into the specified register.
+///
+void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ Constant *C, unsigned R) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
+ unsigned Class = getClass(C->getType());
+ switch (Class) {
+ case cByte:
+ BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
+ return;
+ case cShort: {
+ unsigned TmpReg = makeAnotherReg (C->getType ());
+ BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
+ BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
+ return;
+ }
+ case cInt: {
+ unsigned TmpReg = makeAnotherReg (C->getType ());
+ BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
+ BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
+ return;
+ }
+ default:
+ assert (0 && "Can't copy this kind of constant into register yet");
+ return;
+ }
+ }
+
+ assert (0 && "Can't copy this kind of constant into register yet");
+}
bool V8ISel::runOnFunction(Function &Fn) {
// First pass over the function, lower any unknown intrinsic functions
@@ -112,12 +227,73 @@
void V8ISel::visitReturnInst(ReturnInst &I) {
- if (I.getNumOperands() == 0) {
- // Just emit a 'ret' instruction
- BuildMI(BB, V8::JMPLi, 2, V8::G0).addZImm(8).addReg(V8::I7);
- return;
+ if (I.getNumOperands () == 1) {
+ unsigned RetValReg = getReg (I.getOperand (0));
+ switch (getClass (I.getOperand (0)->getType ())) {
+ case cByte:
+ case cShort:
+ case cInt:
+ // Schlep it over into i0 (where it will become o0 after restore).
+ BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
+ break;
+ default:
+ visitInstruction (I);
+ return;
+ }
+ } else if (I.getNumOperands () != 1) {
+ visitInstruction (I);
+ }
+ // Just emit a 'retl' instruction to return.
+ BuildMI(BB, V8::RETL, 0);
+ return;
+}
+
+void V8ISel::visitBinaryOperator (BinaryOperator &I) {
+ unsigned DestReg = getReg (I);
+ unsigned Op0Reg = getReg (I.getOperand (0));
+ unsigned Op1Reg = getReg (I.getOperand (1));
+
+ unsigned ResultReg = makeAnotherReg (I.getType ());
+ switch (I.getOpcode ()) {
+ case Instruction::Add:
+ BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
+ break;
+ case Instruction::Sub:
+ BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
+ break;
+ default:
+ visitInstruction (I);
+ return;
+ }
+
+ switch (getClass (I.getType ())) {
+ case cByte:
+ if (I.getType ()->isSigned ()) { // add byte
+ BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
+ } else { // add ubyte
+ unsigned TmpReg = makeAnotherReg (I.getType ());
+ BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
+ BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
+ }
+ break;
+ case cShort:
+ if (I.getType ()->isSigned ()) { // add short
+ unsigned TmpReg = makeAnotherReg (I.getType ());
+ BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
+ BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
+ } else { // add ushort
+ unsigned TmpReg = makeAnotherReg (I.getType ());
+ BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
+ BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
+ }
+ break;
+ case cInt:
+ BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (ResultReg);
+ break;
+ default:
+ visitInstruction (I);
+ return;
}
- visitInstruction(I);
}
Index: llvm/lib/Target/SparcV8/SparcV8.h
diff -u llvm/lib/Target/SparcV8/SparcV8.h:1.2.2.1 llvm/lib/Target/SparcV8/SparcV8.h:1.2.2.2
--- llvm/lib/Target/SparcV8/SparcV8.h:1.2.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8.h Wed Mar 10 19:03:49 2004
@@ -23,8 +23,8 @@
class TargetMachine;
FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
-// FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
-// TargetMachine &TM);
+ FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
+ TargetMachine &TM);
} // end namespace llvm;
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.1.2.1 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.1.2.2
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.1.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Wed Mar 10 19:03:49 2004
@@ -46,23 +46,48 @@
let Name = "ADJCALLSTACKUP";
}
-// Section B.20: SAVE and RESTORE - p117
-def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
-def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
-def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
-def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
+// Section A.3 - Synthetic Instructions, p. 85
+let isReturn = 1, isTerminator = 1, simm13 = 8 in
+ def RET : F3_2<2, 0b111000, "ret">;
+let isReturn = 1, isTerminator = 1, simm13 = 8 in
+ def RETL : F3_2<2, 0b111000, "retl">;
-// Section B.24: Call and Link - p125
+// Section B.9 - SETHI Instruction, p. 104
+def SETHIi: F2_1<0b100, "sethi">;
+
+// Section B.11 - Logical Instructions, p. 106
+def ANDri : F3_2<2, 0b000001, "and">;
+def ORrr : F3_1<2, 0b000010, "or">;
+def ORri : F3_2<2, 0b000010, "or">;
+
+// Section B.12 - Shift Instructions, p. 107
+def SLLri : F3_1<2, 0b100101, "sll">;
+def SRLri : F3_1<2, 0b100110, "srl">;
+def SRAri : F3_1<2, 0b100111, "sra">;
+
+// Section B.13 - Add Instructions, p. 108
+def ADDrr : F3_1<2, 0b000000, "add">;
+
+// Section B.15 - Subtract Instructions, p. 110
+def SUBrr : F3_1<2, 0b000100, "sub">;
+
+// Section B.20 - SAVE and RESTORE, p. 117
+def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
+def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
+def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
+def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
+
+// Section B.24 - Call and Link, p. 125
// This is the only Format 1 instruction
def CALL : InstV8 {
bits<30> disp;
-
let op = 1;
let Inst{29-0} = disp;
let Name = "call";
+ let isCall = 1;
}
-// Section B.25: Jump and Link - p126
-def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
-def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
+// Section B.25 - Jump and Link, p. 126
+def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
+def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.3.2.1 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.3.2.2
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.3.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp Wed Mar 10 19:03:49 2004
@@ -71,15 +71,15 @@
// Eventually this should emit the correct save instruction based on the
// number of bytes in the frame. For now we just hardcode it.
- BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
+ BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, V8::SP).addImm(-112).addReg(V8::SP);
}
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == V8::JMPLi &&
- "Can only put epilog before return instruction!");
- BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
+ assert(MBBI->getOpcode() == V8::RETL &&
+ "Can only put epilog before 'retl' instruction!");
+ BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
}
@@ -88,9 +88,8 @@
const TargetRegisterClass*
SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getPrimitiveID()) {
- case Type::FloatTyID:
- case Type::DoubleTyID:
- assert(0 && "Floating point registers not supported yet!");
+ case Type::FloatTyID: return &FPRegsInstance;
+ case Type::DoubleTyID: return &DFPRegsInstance;
case Type::LongTyID:
case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
default: assert(0 && "Invalid type to getClass!");
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.3.2.1 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.3.2.2
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.3.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td Wed Mar 10 19:03:49 2004
@@ -11,9 +11,18 @@
//
//===----------------------------------------------------------------------===//
+// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers
class Ri<bits<5> num> : Register {
- field bits<5> Num = num; // Numbers are identified with a 5 bit ID
+ field bits<5> Num = num;
+}
+// Rf - 32-bit floating-point registers
+class Rf<bits<5> num> : Register {
+ field bits<5> Num = num;
+}
+// Rd - Slots in the FP register file for 64-bit floating-point values.
+class Rd<bits<5> num> : Register {
+ field bits<5> Num = num;
}
let Namespace = "V8" in {
@@ -29,17 +38,64 @@
// Standard register aliases.
def SP : Ri<14>; def FP : Ri<30>;
- // Floating-point registers?
- // ...
+ // Floating-point registers:
+ def F0 : Rf< 0>; def F1 : Rf< 1>; def F2 : Rf< 2>; def F3 : Rf< 3>;
+ def F4 : Rf< 4>; def F5 : Rf< 5>; def F6 : Rf< 6>; def F7 : Rf< 7>;
+ def F8 : Rf< 8>; def F9 : Rf< 9>; def F10 : Rf<10>; def F11 : Rf<11>;
+ def F12 : Rf<12>; def F13 : Rf<13>; def F14 : Rf<14>; def F15 : Rf<15>;
+ def F16 : Rf<16>; def F17 : Rf<17>; def F18 : Rf<18>; def F19 : Rf<19>;
+ def F20 : Rf<20>; def F21 : Rf<21>; def F22 : Rf<22>; def F23 : Rf<23>;
+ def F24 : Rf<24>; def F25 : Rf<25>; def F26 : Rf<26>; def F27 : Rf<27>;
+ def F28 : Rf<28>; def F29 : Rf<29>; def F30 : Rf<30>; def F31 : Rf<31>;
+
+ // Aliases of the F* registers used to hold 64-bit fp values (doubles).
+ def D0 : Rd< 0>; def D1 : Rd< 2>; def D2 : Rd< 4>; def D3 : Rd< 6>;
+ def D4 : Rd< 8>; def D5 : Rd<10>; def D6 : Rd<12>; def D7 : Rd<14>;
+ def D8 : Rd<16>; def D9 : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
+ def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
}
-// For fun, specify a register class.
+// Register classes.
//
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
-def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, O6, O7,
+def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
- I0, I1, I2, I3, I4, I5, I6, I7]>;
+ I0, I1, I2, I3, I4, I5,
+ // Non-allocatable regs
+ O6, I6, I7, G0]> {
+ let Methods = [{
+ iterator allocation_order_end(MachineFunction &MF) const {
+ return end()-4; // Don't allocate special registers
+ }
+ }];
+}
+
+def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
+ F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
+ F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
+def DFPRegs : RegisterClass<f64, 8, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15]>;
+
+// Tell the register file generator that the double-fp pseudo-registers
+// alias the registers used for single-fp values.
+def : RegisterAliases<D0, [F0, F1]>;
+def : RegisterAliases<D1, [F2, F3]>;
+def : RegisterAliases<D2, [F4, F5]>;
+def : RegisterAliases<D3, [F6, F7]>;
+def : RegisterAliases<D4, [F8, F9]>;
+def : RegisterAliases<D5, [F10, F11]>;
+def : RegisterAliases<D6, [F12, F13]>;
+def : RegisterAliases<D7, [F14, F15]>;
+def : RegisterAliases<D8, [F16, F17]>;
+def : RegisterAliases<D9, [F18, F19]>;
+def : RegisterAliases<D10, [F20, F21]>;
+def : RegisterAliases<D11, [F22, F23]>;
+def : RegisterAliases<D12, [F24, F25]>;
+def : RegisterAliases<D13, [F26, F27]>;
+def : RegisterAliases<D14, [F28, F29]>;
+def : RegisterAliases<D15, [F30, F31]>;
Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.4.2.1 llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.4.2.2
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.4.2.1 Mon Mar 1 17:58:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp Wed Mar 10 19:03:49 2004
@@ -42,17 +42,22 @@
std::ostream &Out) {
PM.add(createSparcV8SimpleInstructionSelector(*this));
- // Print machine instructions as they are created.
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ // Print machine instructions as they were initially generated.
+ if (PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());
- // <insert assembly code output passes here>
- // This is not a correct asm writer by any means, but at least we see what we
- // are producing.
- PM.add(createMachineFunctionPrinterPass(&Out));
+ // Print machine instructions after register allocation and prolog/epilog
+ // insertion.
+ if (PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ // Output assembly language.
+ PM.add(createSparcV8CodePrinterPass(Out, *this));
+
+ // Delete the MachineInstrs we generated, since they're no longer needed.
PM.add(createMachineCodeDeleter());
return false;
}
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