[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td

[Brian Gaeke]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.td updated: 1.5 -> 1.6

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Log message:

Hack it so we do not try to allocate values to G0.

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Diffs of the changes:  (+1 -1)

Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.5 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.6
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.5	Wed Mar  3 23:15:03 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Fri Mar  5 23:31:32 2004
@@ -61,7 +61,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7, G0,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;