[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86InstrInfo.td

[Alkis Evlogimenos]

Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.75 -> 1.76
X86InstrInfo.td updated: 1.58 -> 1.59

---
Log message:

Add memory operand version of conditional move.


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Diffs of the changes:  (+10 -3)

Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.75 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.76
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.75	Sun Feb 29 02:50:03 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Sat Mar  6 21:19:11 2004
@@ -260,6 +260,9 @@
     case X86::MOV8rr:  NI = MakeRMInst(X86::MOV8rm , FrameIndex, MI); break;
     case X86::MOV16rr: NI = MakeRMInst(X86::MOV16rm, FrameIndex, MI); break;
     case X86::MOV32rr: NI = MakeRMInst(X86::MOV32rm, FrameIndex, MI); break;
+    case X86::CMOVE16rr:  NI = MakeRMInst(X86::CMOVE16rm , FrameIndex, MI); break;
+    case X86::CMOVNE32rr: NI = MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI); break;
+    case X86::CMOVS32rr:  NI = MakeRMInst(X86::CMOVS32rm , FrameIndex, MI); break;
     case X86::ADD8rr:  NI = MakeRMInst(X86::ADD8rm , FrameIndex, MI); break;
     case X86::ADD16rr: NI = MakeRMInst(X86::ADD16rm, FrameIndex, MI); break;
     case X86::ADD32rr: NI = MakeRMInst(X86::ADD32rm, FrameIndex, MI); break;


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.58 llvm/lib/Target/X86/X86InstrInfo.td:1.59
--- llvm/lib/Target/X86/X86InstrInfo.td:1.58	Sun Feb 29 03:19:40 2004
+++ llvm/lib/Target/X86/X86InstrInfo.td	Sat Mar  6 21:19:11 2004
@@ -294,9 +294,12 @@
 
 // Conditional moves.  These are modelled as X = cmovXX Y, Z.  Eventually
 // register allocated to cmovXX XY, Z
-def CMOVE16rr : I<"cmove", 0x44, MRMSrcReg>, TB, OpSize;        // if ==, R16 = R16
-def CMOVNE32rr: I<"cmovne",0x45, MRMSrcReg>, TB;                // if !=, R32 = R32
-def CMOVS32rr : I<"cmovs", 0x48, MRMSrcReg>, TB;                // if signed, R32 = R32
+def CMOVE16rr : I   <"cmove", 0x44, MRMSrcReg>, TB, OpSize;        // if ==, R16 = R16
+def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize;        // if ==, R16 = [mem16]
+def CMOVNE32rr: I   <"cmovne",0x45, MRMSrcReg>, TB;                // if !=, R32 = R32
+def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB;                // if !=, R32 = [mem32]
+def CMOVS32rr : I   <"cmovs", 0x48, MRMSrcReg>, TB;                // if signed, R32 = R32
+def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB;                // if signed, R32 = [mem32]
 
 // unary instructions
 def NEG8r  : I   <"neg", 0xF6, MRM3r>;         // R8  = -R8  = 0-R8
@@ -397,6 +400,7 @@
 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m     >;            // [mem32] ^= imm8
 
 // Shift instructions
+// FIXME: provide shorter instructions when imm8 == 1
 def SHL8rCL  : I     <"shl", 0xD2, MRM4r     >        , UsesCL; // R8  <<= cl
 def SHL16rCL : I     <"shl", 0xD3, MRM4r     >, OpSize, UsesCL; // R16 <<= cl
 def SHL32rCL : I     <"shl", 0xD3, MRM4r     >        , UsesCL; // R32 <<= cl