[llvm-commits] [parallel] CVS: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp Makefile MappingInfo.cpp MappingInfo.h SparcV9.burg.in SparcV9.td SparcV9AsmPrinter.cpp SparcV9CodeEmitter.cpp SparcV9FrameInfo.cpp SparcV9FrameInfo.h SparcV9Instr.def SparcV9InstrInfo.cpp SparcV9InstrInfo.h SparcV9InstrSelection.cpp SparcV9InstrSelectionSupport.h SparcV9Internals.h SparcV9JITInfo.h SparcV9PeepholeOpts.cpp SparcV9PreSelection.cpp SparcV9PrologEpilogInserter.cpp SparcV9RegClassInfo.cpp SparcV9RegClassInfo.h SparcV9RegInfo.cpp SparcV9RegInfo.h SparcV9SchedInfo.cpp SparcV9StackSlots.cpp SparcV9TargetMachine.cpp SparcV9TargetMachine.h SparcV9_F2.td SparcV9_F3.td SparcV9_F4.td SparcV9_Reg.td
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:05:38 PST 2004
Changes in directory llvm/lib/Target/SparcV9:
EmitBytecodeToAssembly.cpp updated: 1.12 -> 1.12.4.1
Makefile updated: 1.40 -> 1.40.2.1
MappingInfo.cpp updated: 1.15 -> 1.15.4.1
MappingInfo.h updated: 1.6 -> 1.6.4.1
SparcV9.burg.in updated: 1.11 -> 1.11.4.1
SparcV9.td updated: 1.29 -> 1.29.6.1
SparcV9AsmPrinter.cpp updated: 1.101 -> 1.101.2.1
SparcV9CodeEmitter.cpp updated: 1.49 -> 1.49.2.1
SparcV9FrameInfo.cpp updated: 1.1 -> 1.1.2.1
SparcV9FrameInfo.h updated: 1.1 -> 1.1.2.1
SparcV9Instr.def updated: 1.23 -> 1.23.6.1
SparcV9InstrInfo.cpp updated: 1.59 -> 1.59.2.1
SparcV9InstrInfo.h updated: 1.1 -> 1.1.2.1
SparcV9InstrSelection.cpp updated: 1.130 -> 1.130.2.1
SparcV9InstrSelectionSupport.h updated: 1.13 -> 1.13.4.1
SparcV9Internals.h updated: 1.110 -> 1.110.2.1
SparcV9JITInfo.h updated: 1.3 -> 1.3.2.1
SparcV9PeepholeOpts.cpp updated: 1.17 -> 1.17.2.1
SparcV9PreSelection.cpp updated: 1.27 -> 1.27.2.1
SparcV9PrologEpilogInserter.cpp updated: 1.32 -> 1.32.4.1
SparcV9RegClassInfo.cpp updated: 1.34 -> 1.34.2.1
SparcV9RegClassInfo.h updated: 1.23 -> 1.23.4.1
SparcV9RegInfo.cpp updated: 1.116 -> 1.116.2.1
SparcV9RegInfo.h updated: 1.8 -> 1.8.2.1
SparcV9SchedInfo.cpp updated: 1.9 -> 1.9.2.1
SparcV9StackSlots.cpp updated: 1.9 -> 1.9.4.1
SparcV9TargetMachine.cpp updated: 1.98 -> 1.98.2.1
SparcV9TargetMachine.h updated: 1.4 -> 1.4.2.1
SparcV9_F2.td updated: 1.8 -> 1.8.6.1
SparcV9_F3.td updated: 1.17 -> 1.17.6.1
SparcV9_F4.td updated: 1.10 -> 1.10.6.1
SparcV9_Reg.td updated: 1.7 -> 1.7.4.1
---
Log message:
Merge from trunk
---
Diffs of the changes: (+861 -924)
Index: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
diff -u llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.12 llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.12.4.1
--- llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.12 Wed Nov 12 18:19:02 2003
+++ llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to Sparc .s File --------==//
+//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to SparcV9 .s File --------==//
//
// The LLVM Compiler Infrastructure
//
@@ -13,7 +13,7 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
#include "llvm/Pass.h"
#include "llvm/Bytecode/Writer.h"
#include <iostream>
@@ -86,13 +86,13 @@
<< "\n";
}
- // SparcBytecodeWriter - Write bytecode out to a stream that is sparc'ified
- class SparcBytecodeWriter : public Pass {
+ // SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified
+ class SparcV9BytecodeWriter : public Pass {
std::ostream &Out;
public:
- SparcBytecodeWriter(std::ostream &out) : Out(out) {}
+ SparcV9BytecodeWriter(std::ostream &out) : Out(out) {}
- const char *getPassName() const { return "Emit Bytecode to Sparc Assembly";}
+ const char *getPassName() const { return "Emit Bytecode to SparcV9 Assembly";}
virtual bool run(Module &M) {
// Write an object containing the bytecode to the SPARC assembly stream
@@ -113,7 +113,7 @@
} // end anonymous namespace
Pass *createBytecodeAsmPrinterPass(std::ostream &Out) {
- return new SparcBytecodeWriter(Out);
+ return new SparcV9BytecodeWriter(Out);
}
} // End llvm namespace
Index: llvm/lib/Target/SparcV9/Makefile
diff -u llvm/lib/Target/SparcV9/Makefile:1.40 llvm/lib/Target/SparcV9/Makefile:1.40.2.1
--- llvm/lib/Target/SparcV9/Makefile:1.40 Fri Jan 9 12:15:22 2004
+++ llvm/lib/Target/SparcV9/Makefile Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
+##===- lib/Target/SparcV9/Makefile ---------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
@@ -7,10 +7,10 @@
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
-LIBRARYNAME = sparc
+LIBRARYNAME = sparcv9
DIRS = InstrSelection RegAlloc LiveVar
-ExtraSource = Sparc.burm.cpp
+ExtraSource = SparcV9.burm.cpp
include $(LEVEL)/Makefile.common
@@ -20,26 +20,26 @@
DEBUG_FLAG = -D_DEBUG
endif
-Sparc.burg.in1 : $(SourceDir)/Sparc.burg.in
+SparcV9.burg.in1 : $(SourceDir)/SparcV9.burg.in
$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
-Sparc.burm : Sparc.burg.in1
+SparcV9.burm : SparcV9.burg.in1
$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
-Sparc.burm.cpp: Sparc.burm
+SparcV9.burm.cpp: SparcV9.burm
@echo "Burging `basename $<`"
$(RunBurg) $< -o $@
-$(BUILD_OBJ_DIR)/Debug/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Debug/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileG) $< -o $@
-$(BUILD_OBJ_DIR)/Release/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Release/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileO) $< -o $@
-$(BUILD_OBJ_DIR)/Profile/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Profile/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileP) $< -o $@
-$(BUILD_OBJ_DIR)/Depend/Sparc.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
+$(BUILD_OBJ_DIR)/Depend/SparcV9.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
touch $@
TARGET_NAME := SparcV9
@@ -56,5 +56,5 @@
$(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
clean::
- $(RM) -f $(TARGET_NAME)CodeEmitter.inc Sparc.burg.in1 Sparc.burm Sparc.burm.cpp
+ $(RM) -f $(TARGET_NAME)CodeEmitter.inc SparcV9.burg.in1 SparcV9.burm SparcV9.burm.cpp
Index: llvm/lib/Target/SparcV9/MappingInfo.cpp
diff -u llvm/lib/Target/SparcV9/MappingInfo.cpp:1.15 llvm/lib/Target/SparcV9/MappingInfo.cpp:1.15.4.1
--- llvm/lib/Target/SparcV9/MappingInfo.cpp:1.15 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/MappingInfo.cpp Mon Mar 1 17:58:14 2004
@@ -153,7 +153,7 @@
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
BI != BE; ++BI) {
MachineBasicBlock &miBB = *BI;
- key[miBB[0]] = i;
+ key[&miBB.front()] = i;
i = i+(miBB.size());
}
}
@@ -174,7 +174,7 @@
unsigned j = 0;
for(MachineBasicBlock::iterator miI = miBB.begin(), miE = miBB.end();
miI != miE; ++miI, ++j) {
- key[*miI] = j;
+ key[miI] = j;
}
}
}
@@ -195,7 +195,7 @@
BI != BE; ++BI, ++bb) {
MachineBasicBlock &miBB = *BI;
writeNumber(bb);
- writeNumber(BBkey[miBB[0]]);
+ writeNumber(BBkey[&miBB.front()]);
writeNumber(miBB.size());
}
}
Index: llvm/lib/Target/SparcV9/MappingInfo.h
diff -u llvm/lib/Target/SparcV9/MappingInfo.h:1.6 llvm/lib/Target/SparcV9/MappingInfo.h:1.6.4.1
--- llvm/lib/Target/SparcV9/MappingInfo.h:1.6 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/MappingInfo.h Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===- lib/Target/Sparc/MappingInfo.h ---------------------------*- C++ -*-===//
+//===- lib/Target/SparcV9/MappingInfo.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
Index: llvm/lib/Target/SparcV9/SparcV9.burg.in
diff -u llvm/lib/Target/SparcV9/SparcV9.burg.in:1.11 llvm/lib/Target/SparcV9/SparcV9.burg.in:1.11.4.1
--- llvm/lib/Target/SparcV9/SparcV9.burg.in:1.11 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/SparcV9.burg.in Mon Mar 1 17:58:14 2004
@@ -46,7 +46,7 @@
%term Or=OrOPCODE
%term Xor=XorOPCODE
/* Use the next 4 to distinguish bitwise operators from
- * logical operators. This is no longer used for Sparc,
+ * logical operators. This is no longer used for SparcV9,
* but may be useful for other target machines.
* The last one is the bitwise Not(val) == XOR val, 11..1.
* Note that it is also a binary operator, not unary.
Index: llvm/lib/Target/SparcV9/SparcV9.td
diff -u llvm/lib/Target/SparcV9/SparcV9.td:1.29 llvm/lib/Target/SparcV9/SparcV9.td:1.29.6.1
--- llvm/lib/Target/SparcV9/SparcV9.td:1.29 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/SparcV9/SparcV9.td Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===- SparcV9.td - Target Description for Sparc V9 Target ----------------===//
+//===- SparcV9.td - Target Description for SparcV9 V9 Target ----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,7 +19,7 @@
// Instructions
//===----------------------------------------------------------------------===//
-class InstV9 : Instruction { // Sparc instruction baseline
+class InstV9 : Instruction { // SparcV9 instruction baseline
field bits<32> Inst;
let Namespace = "V9";
@@ -27,7 +27,7 @@
bits<2> op;
let Inst{31-30} = op; // Top two bits are the 'op' field
- // Bit attributes specific to Sparc instructions
+ // Bit attributes specific to SparcV9 instructions
bit isPasi = 0; // Does this instruction affect an alternate addr space?
bit isDeprecated = 0; // Is this instruction deprecated?
bit isPrivileged = 0; // Is this a privileged instruction?
@@ -62,7 +62,7 @@
}
// Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
-// The following deprecated instructions don't seem to play nice on Sparc
+// The following deprecated instructions don't seem to play nice on SparcV9
/*
let isDeprecated = 1 in {
let op2 = 0b110 in {
@@ -107,7 +107,7 @@
}
// Section A.5: Branch on FP condition codes with prediction - p143
-// Not used in the Sparc backend (directly)
+// Not used in the SparcV9 backend (directly)
/*
let op2 = 0b101 in {
def FBPA : F2_3<0b1000, "fba">; // Branch always
@@ -176,7 +176,7 @@
}
// Section A.7: Branch on integer condition codes with prediction - p148
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
/*
let op2 = 0b001 in {
def BPA : F2_3<0b1000, "bpa">; // Branch always
@@ -212,7 +212,7 @@
// Section A.10: Divide (64-bit / 32-bit) - p178
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
/*
let isDeprecated = 1 in {
def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
@@ -227,7 +227,7 @@
*/
// Section A.11: DONE and RETRY - p181
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
/*
let isPrivileged = 1 in {
def DONE : F3_18<0, "done">; // done
@@ -247,7 +247,7 @@
def FCMPS : F3_15<2, 0b110101, 0b001010001, "fcmps">; // fcmps %fcc, r1, r2
def FCMPD : F3_15<2, 0b110101, 0b001010010, "fcmpd">; // fcmpd %fcc, r1, r2
def FCMPQ : F3_15<2, 0b110101, 0b001010011, "fcmpq">; // fcmpq %fcc, r1, r2
-// Currently unused in the Sparc backend
+// Currently unused in the SparcV9 backend
/*
def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">; // fcmpes %fcc, r1, r2
def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">; // fcmped %fcc, r1, r2
@@ -317,7 +317,7 @@
// Not currently used
// Section A.24: Jump and Link - p172
-// Mimicking the Sparc's instr def...
+// Mimicking the SparcV9's instr def...
def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
@@ -393,7 +393,7 @@
def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc rs1, imm, rd
// Section A.32: Memory Barrier - p186
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.33: Move Floating-Point Register on Condition (FMOVcc)
// ======================= Single Floating Point ======================
@@ -622,7 +622,7 @@
def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r
// Section A.38: Multiply (32-bit) - p200
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
/*
let Inst{13} = 0 in {
def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
@@ -639,7 +639,7 @@
*/
// Section A.39: Multiply Step - p202
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.40: No operation - p204
// NOP is really a pseudo-instruction (special case of SETHI)
@@ -652,13 +652,13 @@
}
// Section A.41: Population Count - p205
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.42: Prefetch Data - p206
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.43: Read Privileged Register - p211
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.44: Read State Register
// The only instr from this section currently used is RDCCR
@@ -679,7 +679,7 @@
def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
// Section A.47: SAVED and RESTORED - p219
-// Not currently used in Sparc backend
+// Not currently used in SparcV9 backend
// Section A.48: SETHI - p220
let op2 = 0b100 in {
@@ -687,7 +687,7 @@
}
// Section A.49: Shift - p221
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
/*
uses 5 least significant bits of rs2
let x = 0 in {
@@ -720,10 +720,10 @@
def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
// Section A.50: Sofware-Initiated Reset - p223
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.51: Store Barrier - p224
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.52: Store Floating-point - p225
// Store instructions all want their rd register first
@@ -732,7 +732,7 @@
def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
/*
def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
@@ -740,7 +740,7 @@
// FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
// while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
-// These are being disabled because they aren't used in the Sparc backend.
+// These are being disabled because they aren't used in the SparcV9 backend.
/*
let isDeprecated = 1 in {
def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r]
@@ -751,7 +751,7 @@
def STXFSRi : F3_2<3, 0b100101, "stx">; // stx %fsr, [r+i]
// Section A.53: Store Floating-Point into Alternate Space - p227
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.54: Store Integer - p229
// Store instructions all want their rd register first
@@ -765,7 +765,7 @@
def STXi : F3_2rd<3, 0b001110, "stx">; // stx r, [r+i]
// Section A.55: Store Integer into Alternate Space - p231
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
// Section A.56: Subtract - p233
def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.101 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.101.2.1
--- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.101 Thu Jan 15 16:44:19 2004
+++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===-- EmitAssembly.cpp - Emit Sparc Specific .s File ---------------------==//
+//===-- EmitAssembly.cpp - Emit SparcV9 Specific .s File ---------------------==//
//
// The LLVM Compiler Infrastructure
//
@@ -30,7 +30,7 @@
#include "llvm/Support/Mangler.h"
#include "Support/StringExtras.h"
#include "Support/Statistic.h"
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
#include <string>
using namespace llvm;
@@ -119,7 +119,7 @@
///
inline unsigned int
SizeToAlignment(unsigned int size, const TargetMachine& target) {
- unsigned short cacheLineSize = target.getCacheInfo().getCacheLineSize(1);
+ const unsigned short cacheLineSize = 16;
if (size > (unsigned) cacheLineSize / 2)
return cacheLineSize;
else
@@ -184,14 +184,11 @@
}
void PrintZeroBytesToPad(int numBytes) {
- for (/* no init */; numBytes >= 8; numBytes -= 8)
- printSingleConstantValue(Constant::getNullValue(Type::ULongTy));
-
- if (numBytes >= 4) {
- printSingleConstantValue(Constant::getNullValue(Type::UIntTy));
- numBytes -= 4;
- }
-
+ //
+ // Always use single unsigned bytes for padding. We don't know upon
+ // what data size the beginning address is aligned, so using anything
+ // other than a byte may cause alignment errors in the assembler.
+ //
while (numBytes--)
printSingleConstantValue(Constant::getNullValue(Type::UByteTy));
}
@@ -254,7 +251,7 @@
}
// getID Wrappers - Ensure consistent usage
- // Symbol names in Sparc assembly language have these rules:
+ // Symbol names in SparcV9 assembly language have these rules:
// (a) Must match { letter | _ | . | $ } { letter | _ | . | $ | digit }*
// (b) A name beginning in "." is treated as a local name.
std::string getID(const Function *F) {
@@ -343,6 +340,8 @@
toAsm << "\t! " << CV->getType()->getDescription()
<< " value: " << Val << "\n";
+ } else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
+ toAsm << (int)CB->getValue() << "\n";
} else {
WriteAsOperand(toAsm, CV, false, false) << "\n";
}
@@ -388,8 +387,9 @@
}
assert(sizeSoFar == cvsLayout->StructSize &&
"Layout of constant struct may be incorrect!");
- }
- else
+ } else if (isa<ConstantAggregateZero>(CV)) {
+ PrintZeroBytesToPad(Target.getTargetData().getTypeSize(CV->getType()));
+ } else
printSingleConstantValue(CV);
if (numPadBytesAfter)
@@ -504,19 +504,19 @@
//===----------------------------------------------------------------------===//
-// SparcAsmPrinter Code
+// SparcV9AsmPrinter Code
//===----------------------------------------------------------------------===//
namespace {
- struct SparcAsmPrinter : public FunctionPass, public AsmPrinter {
- inline SparcAsmPrinter(std::ostream &os, const TargetMachine &t)
+ struct SparcV9AsmPrinter : public FunctionPass, public AsmPrinter {
+ inline SparcV9AsmPrinter(std::ostream &os, const TargetMachine &t)
: AsmPrinter(os, t) {}
const Function *currFunction;
const char *getPassName() const {
- return "Output Sparc Assembly for Functions";
+ return "Output SparcV9 Assembly for Functions";
}
virtual bool doInitialization(Module &M) {
@@ -565,9 +565,9 @@
} // End anonymous namespace
inline bool
-SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
+SparcV9AsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
unsigned int opNum) {
- switch (MI->getOpCode()) {
+ switch (MI->getOpcode()) {
case V9::JMPLCALLr:
case V9::JMPLCALLi:
case V9::JMPLRETr:
@@ -579,11 +579,11 @@
}
inline bool
-SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
+SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
unsigned int opNum) {
- if (Target.getInstrInfo().isLoad(MI->getOpCode()))
+ if (Target.getInstrInfo().isLoad(MI->getOpcode()))
return (opNum == 0);
- else if (Target.getInstrInfo().isStore(MI->getOpCode()))
+ else if (Target.getInstrInfo().isStore(MI->getOpcode()))
return (opNum == 1);
else
return false;
@@ -596,27 +596,27 @@
printOneOperand(mop2, opCode);
unsigned int
-SparcAsmPrinter::printOperands(const MachineInstr *MI,
+SparcV9AsmPrinter::printOperands(const MachineInstr *MI,
unsigned int opNum)
{
const MachineOperand& mop = MI->getOperand(opNum);
if (OpIsBranchTargetLabel(MI, opNum)) {
- PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+ PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
return 2;
} else if (OpIsMemoryAddressBase(MI, opNum)) {
toAsm << "[";
- PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+ PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
toAsm << "]";
return 2;
} else {
- printOneOperand(mop, MI->getOpCode());
+ printOneOperand(mop, MI->getOpcode());
return 1;
}
}
void
-SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
+SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
MachineOpCode opCode)
{
bool needBitsFlag = true;
@@ -638,7 +638,7 @@
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_MachineRegister:
{
- int regNum = (int)mop.getAllocatedRegNum();
+ int regNum = (int)mop.getReg();
if (regNum == Target.getRegInfo().getInvalidRegNum()) {
// better to print code with NULL registers than to die
@@ -659,7 +659,7 @@
case MachineOperand::MO_PCRelativeDisp:
{
const Value *Val = mop.getVRegValue();
- assert(Val && "\tNULL Value in SparcAsmPrinter");
+ assert(Val && "\tNULL Value in SparcV9AsmPrinter");
if (const BasicBlock *BB = dyn_cast<BasicBlock>(Val))
toAsm << getID(BB);
@@ -670,7 +670,7 @@
else if (const Constant *CV = dyn_cast<Constant>(Val))
toAsm << getID(CV);
else
- assert(0 && "Unrecognized value in SparcAsmPrinter");
+ assert(0 && "Unrecognized value in SparcV9AsmPrinter");
break;
}
@@ -691,8 +691,8 @@
toAsm << ")";
}
-void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
- unsigned Opcode = MI->getOpCode();
+void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
+ unsigned Opcode = MI->getOpcode();
if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
return; // IGNORE PHI NODES
@@ -715,18 +715,18 @@
++EmittedInsts;
}
-void SparcAsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
+void SparcV9AsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
// Emit a label for the basic block
toAsm << getID(MBB.getBasicBlock()) << ":\n";
// Loop over all of the instructions in the basic block...
for (MachineBasicBlock::const_iterator MII = MBB.begin(), MIE = MBB.end();
MII != MIE; ++MII)
- emitMachineInst(*MII);
+ emitMachineInst(MII);
toAsm << "\n"; // Separate BB's with newlines
}
-void SparcAsmPrinter::emitFunction(const Function &F) {
+void SparcV9AsmPrinter::emitFunction(const Function &F) {
std::string methName = getID(&F);
toAsm << "!****** Outputing Function: " << methName << " ******\n";
@@ -760,7 +760,7 @@
toAsm << "\n\n";
}
-void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
+void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
if (GV->hasExternalLinkage())
toAsm << "\t.global\t" << getID(GV) << "\n";
@@ -776,7 +776,7 @@
}
}
-void SparcAsmPrinter::emitGlobals(const Module &M) {
+void SparcV9AsmPrinter::emitGlobals(const Module &M) {
// Output global variables...
for (Module::const_giterator GI = M.gbegin(), GE = M.gend(); GI != GE; ++GI)
if (! GI->isExternal()) {
@@ -796,5 +796,5 @@
FunctionPass *llvm::createAsmPrinterPass(std::ostream &Out,
const TargetMachine &TM) {
- return new SparcAsmPrinter(Out, TM);
+ return new SparcV9AsmPrinter(Out, TM);
}
Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.49 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.49.2.1
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.49 Sat Dec 20 03:17:40 2003
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Mon Mar 1 17:58:14 2004
@@ -34,9 +34,9 @@
#include "Support/Debug.h"
#include "Support/hash_set"
#include "Support/Statistic.h"
-#include "SparcInternals.h"
-#include "SparcTargetMachine.h"
-#include "SparcRegInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9TargetMachine.h"
+#include "SparcV9RegInfo.h"
#include "SparcV9CodeEmitter.h"
#include "Config/alloca.h"
@@ -48,12 +48,12 @@
Statistic<> CallbackCalls("callback", "Number CompilationCallback() calls");
}
-bool SparcTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
MachineCodeEmitter *M = &MCE;
DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE));
PM.add(new SparcV9CodeEmitter(*this, *M));
- PM.add(createSparcMachineCodeDestructionPass()); //Free stuff no longer needed
+ PM.add(createSparcV9MachineCodeDestructionPass()); //Free stuff no longer needed
return false;
}
@@ -179,8 +179,8 @@
void JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
static const unsigned
- o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
- g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
+ o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0,
+ g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
MachineInstr* BinaryCode[] = {
//
@@ -362,7 +362,7 @@
// Rewrite the call target so that we don't fault every time we execute it.
//
- static const unsigned o6 = SparcIntRegClass::o6;
+ static const unsigned o6 = SparcV9IntRegClass::o6;
// Subtract enough to overwrite up to the 'save' instruction
// This depends on whether we made a short call (1 instruction) or the
@@ -418,11 +418,11 @@
DEBUG(std::cerr << "Emitting stub at addr: 0x"
<< std::hex << MCE.getCurrentPCValue() << "\n");
- unsigned o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
+ unsigned o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0;
// restore %g0, 0, %g0
MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
- .addMReg(g0, MOTy::Def);
+ .addMReg(g0, MachineOperand::Def);
SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*R));
delete R;
@@ -485,8 +485,8 @@
fakeReg = RI.getClassRegNum(fakeReg, regClass);
switch (regClass) {
- case SparcRegInfo::IntRegClassID: {
- // Sparc manual, p31
+ case SparcV9RegInfo::IntRegClassID: {
+ // SparcV9 manual, p31
static const unsigned IntRegMap[] = {
// "o0", "o1", "o2", "o3", "o4", "o5", "o7",
8, 9, 10, 11, 12, 13, 15,
@@ -503,14 +503,14 @@
return IntRegMap[fakeReg];
break;
}
- case SparcRegInfo::FloatRegClassID: {
+ case SparcV9RegInfo::FloatRegClassID: {
DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
- if (regType == SparcRegInfo::FPSingleRegType) {
+ if (regType == SparcV9RegInfo::FPSingleRegType) {
// only numbered 0-31, hence can already fit into 5 bits (and 6)
DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
- } else if (regType == SparcRegInfo::FPDoubleRegType) {
+ } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
// FIXME: This assumes that we only have 5-bit register fields!
- // From Sparc Manual, page 40.
+ // From SparcV9 Manual, page 40.
// The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
fakeReg |= (fakeReg >> 5) & 1;
fakeReg &= 0x1f;
@@ -518,7 +518,7 @@
}
return fakeReg;
}
- case SparcRegInfo::IntCCRegClassID: {
+ case SparcV9RegInfo::IntCCRegClassID: {
/* xcc, icc, ccr */
static const unsigned IntCCReg[] = { 6, 4, 2 };
@@ -527,7 +527,7 @@
DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
return IntCCReg[fakeReg];
}
- case SparcRegInfo::FloatCCRegClassID: {
+ case SparcV9RegInfo::FloatCCRegClassID: {
/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
return fakeReg;
@@ -542,9 +542,9 @@
// WARNING: if the call used the delay slot to do meaningful work, that's not
// being accounted for, and the behavior will be incorrect!!
inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
- static const unsigned o6 = SparcIntRegClass::o6,
- o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0,
- g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
+ static const unsigned o6 = SparcV9IntRegClass::o6,
+ o7 = SparcV9IntRegClass::o7, g0 = SparcV9IntRegClass::g0,
+ g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
MachineInstr* BinaryCode[] = {
//
@@ -582,7 +582,7 @@
}
}
-void SparcJITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
+void SparcV9JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
assert (TheJITResolver &&
"Can only call replaceMachineCodeForFunction from within JIT");
uint64_t Target = (uint64_t)(intptr_t)New;
@@ -594,11 +594,7 @@
MachineOperand &MO) {
int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
-
- if (MO.isVirtualRegister()) {
- std::cerr << "ERROR: virtual register found in machine code.\n";
- abort();
- } else if (MO.isPCRelativeDisp()) {
+ if (MO.isPCRelativeDisp()) {
DEBUG(std::cerr << "PCRelativeDisp: ");
Value *V = MO.getVRegValue();
if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
@@ -660,13 +656,12 @@
std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
abort();
}
- } else if (MO.isPhysicalRegister() ||
- MO.getType() == MachineOperand::MO_CCRegister)
+ } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
{
- // This is necessary because the Sparc backend doesn't actually lay out
+ // This is necessary because the SparcV9 backend doesn't actually lay out
// registers in the real fashion -- it skips those that it chooses not to
// allocate, i.e. those that are the FP, SP, etc.
- unsigned fakeReg = MO.getAllocatedRegNum();
+ unsigned fakeReg = MO.getReg();
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
<< realRegByClass << " (LLC: "
@@ -682,17 +677,17 @@
MI, MO.isPCRelative());
} else if (MO.isMachineBasicBlock()) {
// Duplicate code of the above case for VirtualRegister, BasicBlock...
- // It should really hit this case, but Sparc backend uses VRegs instead
+ // It should really hit this case, but SparcV9 backend uses VRegs instead
DEBUG(std::cerr << "Saving reference to MBB\n");
const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
} else if (MO.isExternalSymbol()) {
- // Sparc backend doesn't generate this (yet...)
+ // SparcV9 backend doesn't generate this (yet...)
std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
abort();
} else if (MO.isFrameIndex()) {
- // Sparc backend doesn't generate this (yet...)
+ // SparcV9 backend doesn't generate this (yet...)
int FrameIndex = MO.getFrameIndex();
std::cerr << "ERROR: Frame index unhandled.\n";
abort();
@@ -708,13 +703,13 @@
// are used in SPARC assembly. (Some of these make no sense in combination
// with some of the above; we'll trust that the instruction selector
// will not produce nonsense, and not check for valid combinations here.)
- if (MO.isLoBits32()) { // %lo(val) == %lo() in Sparc ABI doc
+ if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
return rv & 0x03ff;
- } else if (MO.isHiBits32()) { // %lm(val) == %hi() in Sparc ABI doc
+ } else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
return (rv >> 10) & 0x03fffff;
- } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in Sparc ABI doc
+ } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
return (rv >> 32) & 0x03ff;
- } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in Sparc ABI doc
+ } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
return rv >> 42;
} else { // (unadorned) val
return rv;
@@ -783,7 +778,7 @@
currBB = MBB.getBasicBlock();
BBLocations[currBB] = MCE.getCurrentPCValue();
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
- unsigned binCode = getBinaryCodeForInstr(**I);
+ unsigned binCode = getBinaryCodeForInstr(*I);
if (binCode == (1 << 30)) {
// this is an invalid call: the addr is out of bounds. that means a code
// sequence has already been emitted, and this is a no-op
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.1 llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.1.2.1
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.1 Wed Dec 17 16:04:00 2003
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
+//===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,18 +16,18 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "SparcFrameInfo.h"
+#include "SparcV9FrameInfo.h"
using namespace llvm;
int
-SparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction&, bool& pos) const {
+SparcV9FrameInfo::getFirstAutomaticVarOffset(MachineFunction&, bool& pos) const {
pos = false; // static stack area grows downwards
return StaticAreaOffsetFromFP;
}
int
-SparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
+SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
{
// ensure no more auto vars are added
mcInfo.getInfo()->freezeAutomaticVarsArea();
@@ -37,7 +37,7 @@
return StaticAreaOffsetFromFP - autoVarsSize;
}
-int SparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
+int SparcV9FrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
MachineFunctionInfo *MFI = mcInfo.getInfo();
MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added
MFI->freezeSpillsArea(); // ensure no more spill slots are added
@@ -50,7 +50,7 @@
}
int
-SparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& pos) const {
+SparcV9FrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& pos) const {
// Dynamic stack area grows downwards starting at top of opt-args area.
// The opt-args, required-args, and register-save areas are empty except
// during calls and traps, so they are shifted downwards on each
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.1 llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.1.2.1
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.1 Wed Dec 17 16:04:00 2003
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.h Mon Mar 1 17:58:14 2004
@@ -1,4 +1,4 @@
-//===-- SparcFrameInfo.h - Define TargetFrameInfo for Sparc -----*- C++ -*-===//
+//===-- SparcV9FrameInfo.h - Define TargetFrameInfo for SparcV9 -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -22,10 +22,10 @@
namespace llvm {
-class SparcFrameInfo: public TargetFrameInfo {
+class SparcV9FrameInfo: public TargetFrameInfo {
const TargetMachine ⌖
public:
- SparcFrameInfo(const TargetMachine &TM)
+ SparcV9FrameInfo(const TargetMachine &TM)
: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
public:
@@ -114,10 +114,10 @@
private:
/*----------------------------------------------------------------------
- This diagram shows the stack frame layout used by llc on Sparc V9.
+ This diagram shows the stack frame layout used by llc on SparcV9 V9.
Note that only the location of automatic variables, spill area,
temporary storage, and dynamically allocated stack area are chosen
- by us. The rest conform to the Sparc V9 ABI.
+ by us. The rest conform to the SparcV9 V9 ABI.
All stack addresses are offset by OFFSET = 0x7ff (2047).
Alignment assumptions and other invariants:
@@ -156,7 +156,7 @@
*----------------------------------------------------------------------*/
- // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
+ // All stack addresses must be offset by 0x7ff (2047) on SparcV9 V9.
static const int OFFSET = (int) 0x7ff;
static const int StackFrameSizeAlignment = 16;
static const int MinStackFrameSize = 176;
Index: llvm/lib/Target/SparcV9/SparcV9Instr.def
diff -u llvm/lib/Target/SparcV9/SparcV9Instr.def:1.23 llvm/lib/Target/SparcV9/SparcV9Instr.def:1.23.6.1
--- llvm/lib/Target/SparcV9/SparcV9Instr.def:1.23 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/SparcV9/SparcV9Instr.def Mon Mar 1 17:58:14 2004
@@ -51,155 +51,155 @@
// Synthetic SPARC assembly opcodes for setting a register to a constant.
// Max immediate constant should be ignored for both these instructions.
// Use a latency > 1 since this may generate as many as 3 instructions.
-I(SETSW, "setsw", 2, 1, 0, true , 0, 2, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
-I(SETUW, "setuw", 2, 1, 0, false, 0, 2, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
-I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
+I(SETSW, "setsw", 2, 1, 0, true , 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
+I(SETUW, "setuw", 2, 1, 0, false, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
+I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
// Set high-order bits of register and clear low-order bits
-I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
+I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, 0)
// Add or add with carry.
-I(ADDr , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(ADDi , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(ADDccr, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(ADDcci, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(ADDCr , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(ADDCi , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(ADDCccr, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(ADDCcci, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
+I(ADDr , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ADDi , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ADDccr, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(ADDcci, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(ADDCr , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ADDCi , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ADDCccr, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(ADDCcci, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
// Subtract or subtract with carry.
-I(SUBr , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SUBi , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SUBccr , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(SUBcci , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(SUBCr , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SUBCi , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SUBCccr, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(SUBCcci, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
+I(SUBr , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(SUBi , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(SUBccr , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(SUBcci , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(SUBCr , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(SUBCi , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(SUBCccr, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
+I(SUBCcci, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
// Integer multiply, signed divide, unsigned divide.
// Note that the deprecated 32-bit multiply and multiply-step are not used.
-I(MULXr , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(MULXi , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SDIVXr, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(SDIVXi, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(UDIVXr, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
-I(UDIVXi, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
+I(MULXr , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
+I(MULXi , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
+I(SDIVXr, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
+I(SDIVXi, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
+I(UDIVXr, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
+I(UDIVXi, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
// Floating point add, subtract, compare.
// Note that destination of FCMP* instructions is operand 0, not operand 2.
-I(FADDS, "fadds", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FADDD, "faddd", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FADDQ, "faddq", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSUBS, "fsubs", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSUBD, "fsubd", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSUBQ, "fsubq", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FCMPS, "fcmps", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(FCMPD, "fcmpd", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
-I(FCMPQ, "fcmpq", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
+I(FADDS, "fadds", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FADDD, "faddd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FADDQ, "faddq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FSUBS, "fsubs", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FSUBD, "fsubd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FSUBQ, "fsubq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
+I(FCMPS, "fcmps", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
+I(FCMPD, "fcmpd", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
+I(FCMPQ, "fcmpq", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
// Floating point multiply or divide.
-I(FMULS , "fmuls", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FMULD , "fmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FMULQ , "fmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSMULD, "fsmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDMULQ, "fdmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDIVS , "fdivs", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDIVD , "fdivd", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDIVQ , "fdivq", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSQRTS, "fsqrts", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSQRTD, "fsqrtd", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSQRTQ, "fsqrtq", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG)
+I(FMULS , "fmuls", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
+I(FMULD , "fmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
+I(FMULQ , "fmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
+I(FSMULD, "fsmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
+I(FDMULQ, "fdmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
+I(FDIVS , "fdivs", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
+I(FDIVD , "fdivd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
+I(FDIVQ , "fdivq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
+I(FSQRTS, "fsqrts", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
+I(FSQRTD, "fsqrtd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
+I(FSQRTQ, "fsqrtq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
// Logical operations
-I(ANDr , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDi , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDccr , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDcci , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDNr , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDNi , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDNccr, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ANDNcci, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-
-I(ORr , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORi , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORccr , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORcci , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORNr , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORNi , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORNccr, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(ORNcci, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-
-I(XORr , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XORi , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XORccr , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XORcci , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XNORr , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XNORi , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XNORccr, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
-I(XNORcci, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
+I(ANDr , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ANDi , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ANDccr , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ANDcci , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ANDNr , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ANDNi , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ANDNccr, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ANDNcci, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+
+I(ORr , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ORi , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ORccr , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ORcci , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ORNr , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ORNi , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(ORNccr, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(ORNcci, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+
+I(XORr , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(XORi , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(XORccr , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(XORcci , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(XNORr , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(XNORi , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
+I(XNORccr, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
+I(XNORcci, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
// Shift operations
-I(SLLr5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SLLi5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLr5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLi5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRAr5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
-I(SRAi5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
-I(SLLXr6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SLLXi6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLXr6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLXi6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRAXr6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
-I(SRAXi6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
+I(SLLr5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SLLi5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SRLr5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SRLi5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SRAr5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SRAi5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
+I(SLLXr6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
+I(SLLXi6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
+I(SRLXr6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
+I(SRLXi6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
+I(SRAXr6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
+I(SRAXi6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
// Floating point move, negate, and abs instructions
-I(FMOVS, "fmovs", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-I(FMOVD, "fmovd", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-//I(FMOVQ, "fmovq", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG)
-I(FNEGS, "fnegs", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-I(FNEGD, "fnegd", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-//I(FNEGQ, "fnegq", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG)
-I(FABSS, "fabss", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-I(FABSD, "fabsd", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG)
-//I(FABSQ, "fabsq", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG)
+I(FMOVS, "fmovs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+I(FMOVD, "fmovd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+//I(FMOVQ, "fmovq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
+I(FNEGS, "fnegs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+I(FNEGD, "fnegd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+//I(FNEGQ, "fnegq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
+I(FABSS, "fabss", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+I(FABSD, "fabsd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
+//I(FABSQ, "fabsq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
// Convert from floating point to floating point formats
-I(FSTOD, "fstod", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FSTOQ, "fstoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDTOS, "fdtos", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FDTOQ, "fdtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FQTOS, "fqtos", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
-I(FQTOD, "fqtod", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG)
+I(FSTOD, "fstod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FSTOQ, "fstoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
+I(FDTOS, "fdtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FDTOQ, "fdtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
+I(FQTOS, "fqtos", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
+I(FQTOD, "fqtod", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
// Convert from floating point to integer formats.
// Note that this accesses both integer and floating point registers.
-I(FSTOX, "fstox", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FDTOX, "fdtox", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FQTOX, "fqtox", 2, 1, 0, false, 0, 2, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FSTOI, "fstoi", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FDTOI, "fdtoi", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FQTOI, "fqtoi", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
+I(FSTOX, "fstox", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FDTOX, "fdtox", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
+I(FQTOX, "fqtox", 2, 1, 0, false, 0, 2, SPARC_FPA, 0)
+I(FSTOI, "fstoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FDTOI, "fdtoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FQTOI, "fqtoi", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
// Convert from integer to floating point formats
// Note that this accesses both integer and floating point registers.
-I(FXTOS, "fxtos", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FXTOD, "fxtod", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FXTOQ, "fxtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FITOS, "fitos", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FITOD, "fitod", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
-I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
+I(FXTOS, "fxtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FXTOD, "fxtod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FXTOQ, "fxtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
+I(FITOS, "fitos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FITOD, "fitod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
+I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
// Branch on integer comparison with zero.
// Latency excludes the delay slot since it can be issued in same cycle.
-I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
-I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
-I(BRLZ , "brlz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
-I(BRNZ , "brnz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
-I(BRGZ , "brgz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
-I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
+I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
+I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
+I(BRLZ , "brlz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
+I(BRNZ , "brnz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
+I(BRGZ , "brgz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
+I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
// Branch on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
@@ -242,219 +242,219 @@
I(FBO , "fbo", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
// Conditional move on integer comparison with zero.
-I(MOVRZr , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRZi , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLEZr, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLEZi, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLZr , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLZi , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRNZr , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRNZi , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGZr , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGZi , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGEZr, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGEZi, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRZr , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRZi , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRLEZr, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRLEZi, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRLZr , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRLZi , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRNZr , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRNZi , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRGZr , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRGZi , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRGEZr, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
+I(MOVRGEZi, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
// Conditional move on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
-I(MOVAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGUr , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVGUi , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLEUr, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVLEUi, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVCCr , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVCCi , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVCSr , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVCSi , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVPOSr, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVPOSi, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNEGr, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVNEGi, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVVCr , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVVCi , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVVSr , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVVSi , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
+I(MOVAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGUr , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVGUi , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLEUr, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVLEUi, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVCCr , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVCCi , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVCSr , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVCSi , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVPOSr, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVPOSi, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNEGr, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVNEGi, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVVCr , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVVCi , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVVSr , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVVSi , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
// Conditional move (of integer register) on floating point condition code.
// The first argument is the FCCn register (0 <= n <= 3).
// Note that the enum name above is not the same as the assembly mnemonic
// because some of the assembly mnemonics are the same as the move on
// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
-I(MOVFAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUr , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUi , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUGr , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUGi , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFULr , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFULi , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLGr , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLGi , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUEr , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUEi , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUGEr, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFUGEi, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFULEr, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFULEi, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFOr , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
-I(MOVFOi , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
+I(MOVFAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUr , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUi , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUGr , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUGi , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFULr , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFULi , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLGr , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLGi , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUEr , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUEi , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUGEr, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFUGEi, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFULEr, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFULEi, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFOr , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(MOVFOi , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
// Conditional move of floating point register on each of the above:
// i. on integer comparison with zero.
// ii. on integer condition code
// iii. on floating point condition code
// Note that the same set is repeated for S,D,Q register classes.
-I(FMOVRSZ ,"fmovrsz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRSLEZ,"fmovrslez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRSLZ ,"fmovrslz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRSNZ ,"fmovrsnz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRSGZ ,"fmovrsgz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRSGEZ,"fmovrsgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-
-I(FMOVSA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSGU , "fmovsgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSLEU, "fmovsleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSCC , "fmovscc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSCS , "fmovscs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSPOS, "fmovspos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSNEG, "fmovsneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSVC , "fmovsvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSVS , "fmovsvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-
-I(FMOVSFA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFU , "fmovsu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFUG , "fmovsug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFUL , "fmovsul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFLG , "fmovslg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFUE , "fmovsue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFUGE, "fmovsuge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFULE, "fmovslue",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVSFO , "fmovso", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-
-I(FMOVRDZ , "fmovrdz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRDLEZ, "fmovrdlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRDLZ , "fmovrdlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRDNZ , "fmovrdnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRDGZ , "fmovrdgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRDGEZ, "fmovrdgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-
-I(FMOVDA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDGU , "fmovdgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDLEU, "fmovdleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDCC , "fmovdcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDCS , "fmovdcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDPOS, "fmovdpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDNEG, "fmovdneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDVC , "fmovdvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDVS , "fmovdvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-
-I(FMOVDFA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFU , "fmovdu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFUG , "fmovdug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFUL , "fmovdul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFLG , "fmovdlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFUE , "fmovdue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFUGE, "fmovduge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFULE, "fmovdule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVDFO , "fmovdo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-
-I(FMOVRQZ , "fmovrqz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRQLEZ, "fmovrqlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRQLZ , "fmovrqlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRQNZ , "fmovrqnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRQGZ , "fmovrqgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-I(FMOVRQGEZ, "fmovrqgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG)
-
-I(FMOVQA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQGU , "fmovqgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQLEU, "fmovqleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQCC , "fmovqcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQCS , "fmovqcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQPOS, "fmovqpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQNEG, "fmovqneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQVC , "fmovqvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQVS , "fmovqvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-
-I(FMOVQFA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFU , "fmovqu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFUG , "fmovqug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFUL , "fmovqul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFLG , "fmovqlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFUE , "fmovque", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFUGE, "fmovquge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFULE, "fmovqule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
-I(FMOVQFO , "fmovqo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
+I(FMOVRSZ ,"fmovrsz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRSLEZ,"fmovrslez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRSLZ ,"fmovrslz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRSNZ ,"fmovrsnz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRSGZ ,"fmovrsgz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRSGEZ,"fmovrsgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+
+I(FMOVSA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSGU , "fmovsgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSLEU, "fmovsleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSCC , "fmovscc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSCS , "fmovscs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSPOS, "fmovspos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSNEG, "fmovsneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSVC , "fmovsvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSVS , "fmovsvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+
+I(FMOVSFA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFU , "fmovsu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFUG , "fmovsug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFUL , "fmovsul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFLG , "fmovslg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFUE , "fmovsue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFUGE, "fmovsuge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFULE, "fmovslue",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVSFO , "fmovso", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+
+I(FMOVRDZ , "fmovrdz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRDLEZ, "fmovrdlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRDLZ , "fmovrdlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRDNZ , "fmovrdnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRDGZ , "fmovrdgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRDGEZ, "fmovrdgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+
+I(FMOVDA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDGU , "fmovdgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDLEU, "fmovdleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDCC , "fmovdcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDCS , "fmovdcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDPOS, "fmovdpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDNEG, "fmovdneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDVC , "fmovdvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDVS , "fmovdvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+
+I(FMOVDFA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFU , "fmovdu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFUG , "fmovdug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFUL , "fmovdul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFLG , "fmovdlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFUE , "fmovdue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFUGE, "fmovduge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFULE, "fmovdule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVDFO , "fmovdo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+
+I(FMOVRQZ , "fmovrqz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRQLEZ, "fmovrqlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRQLZ , "fmovrqlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRQNZ , "fmovrqnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRQGZ , "fmovrqgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+I(FMOVRQGEZ, "fmovrqgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
+
+I(FMOVQA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQGU , "fmovqgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQLEU, "fmovqleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQCC , "fmovqcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQCS , "fmovqcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQPOS, "fmovqpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQNEG, "fmovqneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQVC , "fmovqvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQVS , "fmovqvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+
+I(FMOVQFA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFU , "fmovqu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFUG , "fmovqug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFUL , "fmovqul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFLG , "fmovqlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFUE , "fmovque", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFUGE, "fmovquge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFULE, "fmovqule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
+I(FMOVQFO , "fmovqo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG)
// Load integer instructions
// Latency includes 1 cycle for address generation (Sparc IIi),
@@ -464,55 +464,55 @@
// Not reflected here: After a 3-cycle loads, all subsequent consecutive
// loads also require 3 cycles to avoid contention for the load return
// stage. Latency returns to 2 cycles after the first cycle with no load.
-I(LDSBr, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDSBi, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDSHr, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDSHi, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDSWr, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDSWi, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUBr, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUBi, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUHr, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUHi, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUWr, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDUWi, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDXr , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
-I(LDXi , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
+I(LDSBr, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDSBi, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDSHr, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDSHi, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDSWr, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDSWi, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
+I(LDUBr, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDUBi, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDUHr, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDUHi, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDUWr, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDUWi, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDXr , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDXi , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
// Load floating-point instructions
// Latency includes 1 cycle for address generation (Sparc IIi)
-I(LDFr , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDFi , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDDFr, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDDFi, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDQFr, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDQFi, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDFSRr, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDFSRi, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDXFSRr, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
-I(LDXFSRi, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
+I(LDFr , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDFi , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDDFr, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDDFi, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDQFr, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDQFi, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDFSRr, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDFSRi, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDXFSRr, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
+I(LDXFSRi, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
// Store integer instructions.
// Requires 1 cycle for address generation (Sparc IIi).
// Default latency is 0 because value is not explicitly used.
-I(STBr, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STBi, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STHr, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STHi, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STWr, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STWi, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STXr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
-I(STXi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
+I(STBr, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STBi, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STHr, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STHi, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STWr, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STWi, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STXr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STXi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
// Store floating-point instructions (Sparc IIi)
-I(STFr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STFi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STDFr, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STDFi, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STFSRr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STFSRi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STXFSRr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
-I(STXFSRi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
+I(STFr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STFi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STDFr, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STDFi, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STFSRr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STFSRi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STXFSRr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
+I(STXFSRi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
// Call, Return and "Jump and link". Operand (2) for JMPL is marked as
// a "result" because JMPL stores the return address for the call in it.
@@ -526,19 +526,19 @@
I(RETURNi, "return", 2, -1, 0, false, 1, 2, SPARC_CTI, M_RET_FLAG)
// SAVE and restore instructions
-I(SAVEr, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, M_INT_FLAG | M_ARITH_FLAG)
-I(SAVEi, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, M_INT_FLAG | M_ARITH_FLAG)
-I(RESTOREr, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, M_INT_FLAG | M_ARITH_FLAG)
-I(RESTOREi, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, M_INT_FLAG | M_ARITH_FLAG)
+I(SAVEr, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
+I(SAVEi, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
+I(RESTOREr, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
+I(RESTOREi, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
// Read and Write CCR register from/to an int reg
-I(RDCCR, "rd", 2, 1, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
-I(WRCCRr, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
-I(WRCCRi, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
+I(RDCCR, "rd", 2, 1, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
+I(WRCCRr, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
+I(WRCCRi, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
// Synthetic phi operation for near-SSA form of machine code
// Number of operands is variable, indicated by -1. Result is the first op.
-I(PHI, "<phi>", -1, 0, 0, false, 0, 0, SPARC_INV, M_DUMMY_PHI_FLAG)
+I(PHI, "<phi>", -1, 0, 0, false, 0, 0, SPARC_NONE, M_DUMMY_PHI_FLAG)
#undef B5
Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.59 llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.59.2.1
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.59 Wed Dec 17 16:04:00 2003
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcInstrInfo.cpp ------------------------------------------------===//
+//===-- SparcV9InstrInfo.cpp ------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -20,9 +20,9 @@
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "SparcInternals.h"
-#include "SparcInstrSelectionSupport.h"
-#include "SparcInstrInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9InstrSelectionSupport.h"
+#include "SparcV9InstrInfo.h"
namespace llvm {
@@ -42,7 +42,7 @@
//---------------------------------------------------------------------------
uint64_t
-SparcInstrInfo::ConvertConstantToIntType(const TargetMachine &target,
+SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target,
const Value *V,
const Type *destType,
bool &isValidConstant) const
@@ -386,7 +386,7 @@
default: break;
};
- return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
+ return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
}
static void
@@ -407,26 +407,22 @@
//---------------------------------------------------------------------------
-// class SparcInstrInfo
+// class SparcV9InstrInfo
//
// Purpose:
// Information about individual instructions.
-// Most information is stored in the SparcMachineInstrDesc array above.
+// Most information is stored in the SparcV9MachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
-/*ctor*/
-SparcInstrInfo::SparcInstrInfo()
- : TargetInstrInfo(SparcMachineInstrDesc,
- /*descSize = */ V9::NUM_TOTAL_OPCODES,
- /*numRealOpCodes = */ V9::NUM_REAL_OPCODES)
-{
+SparcV9InstrInfo::SparcV9InstrInfo()
+ : TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) {
InitializeMaxConstantsTable();
}
bool
-SparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
+SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
const Instruction* I) const
{
if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
@@ -456,7 +452,7 @@
// Any stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
+SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@@ -553,7 +549,7 @@
// Any stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
+SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@@ -614,7 +610,7 @@
// Temporary stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
+SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@@ -665,7 +661,7 @@
// Any stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
+SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
Function *F,
Value* src,
Instruction* dest,
@@ -761,7 +757,7 @@
// Any stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateSignExtensionInstructions(
+SparcV9InstrInfo::CreateSignExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,
@@ -783,7 +779,7 @@
// Any stack space required is allocated via MachineFunction.
//
void
-SparcInstrInfo::CreateZeroExtensionInstructions(
+SparcV9InstrInfo::CreateZeroExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,
Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.1 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.1.2.1
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.1 Wed Dec 17 16:04:00 2003
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcInstrInfo.h - Define TargetInstrInfo for Sparc -----*- C++ -*-===//
+//===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//
// This class contains information about individual instructions.
-// Most information is stored in the SparcMachineInstrDesc array above.
+// Most information is stored in the SparcV9MachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class TargetInstrInfo.
//
@@ -19,12 +19,12 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
namespace llvm {
-struct SparcInstrInfo : public TargetInstrInfo {
- SparcInstrInfo();
+struct SparcV9InstrInfo : public TargetInstrInfo {
+ SparcV9InstrInfo();
// All immediate constants are in position 1 except the
// store instructions and SETxx.
@@ -48,32 +48,6 @@
return -1;
}
- /// createNOPinstr - returns the target's implementation of NOP, which is
- /// usually a pseudo-instruction, implemented by a degenerate version of
- /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
- ///
- MachineInstr* createNOPinstr() const {
- return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
- }
-
- /// isNOPinstr - not having a special NOP opcode, we need to know if a given
- /// instruction is interpreted as an `official' NOP instr, i.e., there may be
- /// more than one way to `do nothing' but only one canonical way to slack off.
- ///
- bool isNOPinstr(const MachineInstr &MI) const {
- // Make sure the instruction is EXACTLY `sethi g0, 0'
- if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
- const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
- if (op0.isImmediate() && op0.getImmedValue() == 0 &&
- op1.isMachineRegister() &&
- op1.getMachineRegNum() == SparcIntRegClass::g0)
- {
- return true;
- }
- }
- return false;
- }
-
virtual bool hasResultInterlock(MachineOpCode opCode) const
{
// All UltraSPARC instructions have interlocks (note that delay slots
Index: llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.130 llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.130.2.1
--- llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.130 Mon Jan 12 12:08:18 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcInstrSelection.cpp -------------------------------------------===//
+//===-- SparcV9InstrSelection.cpp -------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -23,11 +23,11 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineInstrAnnot.h"
-#include "SparcInstrSelectionSupport.h"
-#include "SparcInternals.h"
-#include "SparcRegClassInfo.h"
-#include "SparcRegInfo.h"
+#include "MachineInstrAnnot.h"
+#include "SparcV9InstrSelectionSupport.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegClassInfo.h"
+#include "SparcV9RegInfo.h"
#include "Support/MathExtras.h"
#include <algorithm>
#include <cmath>
@@ -786,9 +786,9 @@
MachineInstr* M = (optArgVal2 != NULL)
? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
- .addReg(shiftDest, MOTy::Def)
+ .addReg(shiftDest, MachineOperand::Def)
: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
- .addReg(shiftDest, MOTy::Def);
+ .addReg(shiftDest, MachineOperand::Def);
mvec.push_back(M);
if (shiftDest != destVal) {
@@ -874,7 +874,7 @@
if (firstNewInstr < mvec.size()) {
cost = 0;
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
- cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
+ cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode());
}
return cost;
@@ -915,7 +915,7 @@
Value* lval, Value* rval, Instruction* destVal,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi,
- MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
+ MachineOpCode forceMulOp = -1)
{
unsigned L = mvec.size();
CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
@@ -923,7 +923,7 @@
// no instructions were added so create MUL reg, reg, reg.
// Use FSMULD if both operands are actually floats cast to doubles.
// Otherwise, use the default opcode for the appropriate type.
- MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
+ MachineOpCode mulOp = ((forceMulOp != -1)
? forceMulOp
: ChooseMulInstructionByType(destVal->getType()));
mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
@@ -1115,15 +1115,15 @@
// Instruction 1: mul numElements, typeSize -> tmpProd
// This will optimize the MUL as far as possible.
CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd, getMvec,
- mcfi, INVALID_MACHINE_OPCODE);
+ mcfi, -1);
// Instruction 2: andn tmpProd, 0x0f -> tmpAndn
getMvec.push_back(BuildMI(V9::ADDi, 3).addReg(tmpProd).addSImm(15)
- .addReg(tmpAdd15, MOTy::Def));
+ .addReg(tmpAdd15, MachineOperand::Def));
// Instruction 3: add tmpAndn, 0x10 -> tmpAdd16
getMvec.push_back(BuildMI(V9::ANDi, 3).addReg(tmpAdd15).addSImm(-16)
- .addReg(tmpAndf0, MOTy::Def));
+ .addReg(tmpAndf0, MachineOperand::Def));
totalSizeVal = tmpAndf0;
}
@@ -1141,7 +1141,7 @@
// Instruction 2: sub %sp, totalSizeVal -> %sp
getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
- .addMReg(SPReg,MOTy::Def));
+ .addMReg(SPReg,MachineOperand::Def));
// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
@@ -1278,7 +1278,7 @@
eltSizeVal, /* rval, likely to be constant */
addr, /* result */
mulVec, MachineCodeForInstruction::get(memInst),
- INVALID_MACHINE_OPCODE);
+ -1);
assert(mulVec.size() > 0 && "No multiply code created?");
mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
@@ -1413,7 +1413,7 @@
}
case Intrinsic::va_end:
- return true; // no-op on Sparc
+ return true; // no-op on SparcV9
case Intrinsic::va_copy:
// Simple copy of current va_list (arg1) to new va_list (result)
@@ -1534,7 +1534,7 @@
MachineInstr* retMI =
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
- .addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def);
+ .addMReg(target.getRegInfo().getZeroRegNum(), MachineOperand::Def);
// If there is a value to return, we need to:
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
@@ -1543,13 +1543,13 @@
// -- For non-FP values, create an add-with-0 instruction
//
if (retVal != NULL) {
- const SparcRegInfo& regInfo =
- (SparcRegInfo&) target.getRegInfo();
+ const SparcV9RegInfo& regInfo =
+ (SparcV9RegInfo&) target.getRegInfo();
const Type* retType = retVal->getType();
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
unsigned retRegNum = (retType->isFloatingPoint()
- ? (unsigned) SparcFloatRegClass::f0
- : (unsigned) SparcIntRegClass::i0);
+ ? (unsigned) SparcV9FloatRegClass::f0
+ : (unsigned) SparcV9IntRegClass::i0);
retRegNum = regInfo.getUnifiedRegNum(regClassID, retRegNum);
// () Insert sign-extension instructions for small signed values.
@@ -1581,11 +1581,11 @@
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
- .addReg(retValToUse).addReg(retVReg, MOTy::Def));
+ .addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(retType), 3)
.addReg(retValToUse).addSImm((int64_t) 0)
- .addReg(retVReg, MOTy::Def));
+ .addReg(retVReg, MachineOperand::Def));
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, retRegNum);
@@ -1751,7 +1751,7 @@
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
mvec.push_back(BuildMI(V9::MOVRZi, 3).addReg(notArg).addZImm(1)
- .addReg(notI, MOTy::UseAndDef));
+ .addReg(notI, MachineOperand::UseAndDef));
break;
}
@@ -1786,7 +1786,7 @@
// value will be retained if the condition is false.
MachineOpCode opCode = foldCase? V9::MOVRZi : V9::MOVRNZi;
mvec.push_back(BuildMI(opCode, 3).addReg(opVal).addZImm(1)
- .addReg(castI, MOTy::UseAndDef));
+ .addReg(castI, MachineOperand::UseAndDef));
break;
}
@@ -1918,7 +1918,7 @@
const MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(
cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
- if (mcfi.size() == 0 || mcfi.front()->getOpCode() == V9::FSMULD)
+ if (mcfi.size() == 0 || mcfi.front()->getOpcode() == V9::FSMULD)
forwardOperandNum = 0; // forward first operand to user
}
@@ -2006,8 +2006,8 @@
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
- ? V9::FSMULD
- : INVALID_MACHINE_OPCODE);
+ ? (MachineOpCode)V9::FSMULD
+ : -1);
Instruction* mulInstr = subtreeRoot->getInstruction();
CreateMulInstruction(target, mulInstr->getParent()->getParent(),
subtreeRoot->leftChild()->getValue(),
@@ -2024,8 +2024,8 @@
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
- ? V9::FSMULD
- : INVALID_MACHINE_OPCODE);
+ ? (MachineOpCode)V9::FSMULD
+ : -1);
Instruction* mulInstr = subtreeRoot->getInstruction();
CreateMulInstruction(target, mulInstr->getParent()->getParent(),
subtreeRoot->leftChild()->getValue(),
@@ -2149,12 +2149,12 @@
Value *lhs = subtreeRoot->leftChild()->getValue();
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
- .addReg(dest, MOTy::Def));
+ .addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
- .addReg(dest, MOTy::UseAndDef));
+ .addReg(dest, MachineOperand::UseAndDef));
}
break;
@@ -2180,12 +2180,12 @@
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
- .addReg(dest, MOTy::Def));
+ .addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
- .addReg(dest, MOTy::UseAndDef));
+ .addReg(dest, MachineOperand::UseAndDef));
}
break;
@@ -2210,12 +2210,12 @@
Value *lhs = subtreeRoot->leftChild()->getValue();
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
- .addReg(dest, MOTy::Def));
+ .addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
- .addReg(dest, MOTy::UseAndDef));
+ .addReg(dest, MachineOperand::UseAndDef));
}
break;
}
@@ -2262,7 +2262,8 @@
MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
mvec.push_back(BuildMI(movOpCode, 3)
.addReg(subtreeRoot->leftChild()->getValue())
- .addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
+ .addZImm(1)
+ .addReg(setCCInstr, MachineOperand::UseAndDef));
break;
}
@@ -2336,12 +2337,13 @@
mvec.push_back(BuildMI(V9::SUBccr, 4)
.addReg(leftOpToUse)
.addReg(rightOpToUse)
- .addMReg(target.getRegInfo().getZeroRegNum(),MOTy::Def)
- .addCCReg(tmpForCC, MOTy::Def));
+ .addMReg(target.getRegInfo()
+ .getZeroRegNum(), MachineOperand::Def)
+ .addCCReg(tmpForCC, MachineOperand::Def));
} else {
// FP condition: dest of FCMP should be some FCCn register
mvec.push_back(BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
- .addCCReg(tmpForCC, MOTy::Def)
+ .addCCReg(tmpForCC, MachineOperand::Def)
.addReg(leftOpToUse)
.addReg(rightOpToUse));
}
@@ -2359,7 +2361,7 @@
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
M = (BuildMI(movOpCode, 3).addCCReg(tmpForCC).addZImm(1)
- .addReg(setCCInstr, MOTy::UseAndDef));
+ .addReg(setCCInstr, MachineOperand::UseAndDef));
mvec.push_back(M);
}
break;
@@ -2448,8 +2450,8 @@
MachineFunction& MF = MachineFunction::get(currentFunc);
MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(callInstr);
- const SparcRegInfo& regInfo =
- (SparcRegInfo&) target.getRegInfo();
+ const SparcV9RegInfo& regInfo =
+ (SparcV9RegInfo&) target.getRegInfo();
const TargetFrameInfo& frameInfo = target.getFrameInfo();
// Create hidden virtual register for return address with type void*
@@ -2589,7 +2591,7 @@
unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
.addMReg(regInfo.getFramePointer()).addSImm(tmpOffset)
- .addReg(argVReg, MOTy::Def);
+ .addReg(argVReg, MachineOperand::Def);
// Mark operand with register it should be assigned
// both for copy and for the callMI
@@ -2668,11 +2670,11 @@
// -- For non-FP values, create an add-with-0 instruction
if (argType->isFloatingPoint())
M=(BuildMI(argType==Type::FloatTy? V9::FMOVS :V9::FMOVD,2)
- .addReg(argVal).addReg(argVReg, MOTy::Def));
+ .addReg(argVal).addReg(argVReg, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(argType), 3)
.addReg(argVal).addSImm((int64_t) 0)
- .addReg(argVReg, MOTy::Def));
+ .addReg(argVReg, MachineOperand::Def));
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
@@ -2699,8 +2701,8 @@
const Type* retType = callInstr->getType();
int regNum = (retType->isFloatingPoint()
- ? (unsigned) SparcFloatRegClass::f0
- : (unsigned) SparcIntRegClass::o0);
+ ? (unsigned) SparcV9FloatRegClass::f0
+ : (unsigned) SparcV9IntRegClass::o0);
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
regNum = regInfo.getUnifiedRegNum(regClassID, regNum);
@@ -2716,11 +2718,11 @@
// -- For non-FP values, create an add-with-0 instruction
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
- .addReg(retVReg).addReg(callInstr, MOTy::Def));
+ .addReg(retVReg).addReg(callInstr, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(retType), 3)
.addReg(retVReg).addSImm((int64_t) 0)
- .addReg(callInstr, MOTy::Def));
+ .addReg(callInstr, MachineOperand::Def));
// Mark the operand with the register it should be assigned
// Also mark the implicit ref of the call defining this operand
@@ -2878,12 +2880,13 @@
tmpI, NULL, "maskHi2");
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpI)
.addZImm(8*(4-destSize))
- .addReg(srlArgToUse, MOTy::Def));
+ .addReg(srlArgToUse, MachineOperand::Def));
}
// Logical right shift 32-N to get zero extension in top 64-N bits.
mvec.push_back(BuildMI(V9::SRLi5, 3).addReg(srlArgToUse)
- .addZImm(8*(4-destSize)).addReg(dest, MOTy::Def));
+ .addZImm(8*(4-destSize))
+ .addReg(dest, MachineOperand::Def));
} else if (destSize < 8) {
assert(0 && "Unsupported type size: 32 < size < 64 bits");
Index: llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.13 llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.13.4.1
--- llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.13 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/SparcInstrSelectionSupport.h ---------------*- C++ -*-===//
+//===-- llvm/CodeGen/SparcV9InstrSelectionSupport.h ---------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,7 +15,7 @@
#define SPARC_INSTR_SELECTION_SUPPORT_h
#include "llvm/DerivedTypes.h"
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
namespace llvm {
@@ -90,7 +90,7 @@
}
-// Because the Sparc instruction selector likes to re-write operands to
+// Because the SparcV9 instruction selector likes to re-write operands to
// instructions, making them change from a Value* (virtual register) to a
// Constant* (making an immediate field), we need to change the opcode from a
// register-based instruction to an immediate-based instruction, hence this
Index: llvm/lib/Target/SparcV9/SparcV9Internals.h
diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.110 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.110.2.1
--- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.110 Sat Dec 20 03:17:40 2003
+++ llvm/lib/Target/SparcV9/SparcV9Internals.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
+//===-- SparcV9Internals.h ----------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines stuff that is to be private to the Sparc backend, but is
+// This file defines stuff that is to be private to the SparcV9 backend, but is
// shared among different portions of the backend.
//
//===----------------------------------------------------------------------===//
@@ -19,19 +19,18 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSchedInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/TargetCacheInfo.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Type.h"
-#include "SparcRegClassInfo.h"
+#include "SparcV9RegClassInfo.h"
#include "Config/sys/types.h"
namespace llvm {
class LiveRange;
-class SparcTargetMachine;
+class SparcV9TargetMachine;
class Pass;
-enum SparcInstrSchedClass {
+enum SparcV9InstrSchedClass {
SPARC_NONE, /* Instructions with no scheduling restrictions */
SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
SPARC_IEU0, /* Integer class IEU0 */
@@ -49,20 +48,20 @@
//---------------------------------------------------------------------------
-// enum SparcMachineOpCode.
-// const TargetInstrDescriptor SparcMachineInstrDesc[]
+// enum SparcV9MachineOpCode.
+// const TargetInstrDescriptor SparcV9MachineInstrDesc[]
//
// Purpose:
-// Description of UltraSparc machine instructions.
+// Description of UltraSparcV9 machine instructions.
//
//---------------------------------------------------------------------------
namespace V9 {
- enum SparcMachineOpCode {
+ enum SparcV9MachineOpCode {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
ENUM,
-#include "SparcInstr.def"
+#include "SparcV9Instr.def"
// End-of-array marker
INVALID_OPCODE,
@@ -72,36 +71,23 @@
}
// Array of machine instruction descriptions...
-extern const TargetInstrDescriptor SparcMachineInstrDesc[];
+extern const TargetInstrDescriptor SparcV9MachineInstrDesc[];
//---------------------------------------------------------------------------
-// class SparcSchedInfo
+// class SparcV9SchedInfo
//
// Purpose:
// Interface to instruction scheduling information for UltraSPARC.
// The parameter values above are based on UltraSPARC IIi.
//---------------------------------------------------------------------------
-class SparcSchedInfo: public TargetSchedInfo {
+class SparcV9SchedInfo: public TargetSchedInfo {
public:
- SparcSchedInfo(const TargetMachine &tgt);
+ SparcV9SchedInfo(const TargetMachine &tgt);
protected:
virtual void initializeResources();
};
-//---------------------------------------------------------------------------
-// class SparcCacheInfo
-//
-// Purpose:
-// Interface to cache parameters for the UltraSPARC.
-// Just use defaults for now.
-//---------------------------------------------------------------------------
-
-struct SparcCacheInfo: public TargetCacheInfo {
- SparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
-};
-
-
/// createStackSlotsPass - External interface to stack-slots pass that enters 2
/// empty slots at the top of each function stack
///
@@ -127,7 +113,7 @@
///
Pass* createBytecodeAsmPrinterPass(std::ostream &Out);
-FunctionPass *createSparcMachineCodeDestructionPass();
+FunctionPass *createSparcV9MachineCodeDestructionPass();
} // End llvm namespace
Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.3 llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.3.2.1
--- llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.3 Sun Dec 28 15:23:38 2003
+++ llvm/lib/Target/SparcV9/SparcV9JITInfo.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===- SparcJITInfo.h - Sparc implementation of the JIT interface -*-C++-*-===//
+//===- SparcV9JITInfo.h - SparcV9 implementation of the JIT interface -*-C++-*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains the Sparc implementation of the TargetJITInfo class.
+// This file contains the SparcV9 implementation of the TargetJITInfo class.
//
//===----------------------------------------------------------------------===//
@@ -19,10 +19,10 @@
namespace llvm {
class TargetMachine;
- class SparcJITInfo : public TargetJITInfo {
+ class SparcV9JITInfo : public TargetJITInfo {
TargetMachine &TM;
public:
- SparcJITInfo(TargetMachine &tm) : TM(tm) {}
+ SparcV9JITInfo(TargetMachine &tm) : TM(tm) {}
/// addPassesToJITCompile - Add passes to the specified pass manager to
/// implement a fast dynamic compiler for this target. Return true if this
Index: llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.17 llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.17.2.1
--- llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.17 Wed Dec 17 16:08:20 2003
+++ llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp Mon Mar 1 17:58:15 2004
@@ -12,13 +12,14 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "Support/STLExtras.h"
namespace llvm {
@@ -31,14 +32,14 @@
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin()) {
const TargetInstrInfo& mii = target.getInstrInfo();
- MachineInstr* predMI = *(BBI-1);
- if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode())) {
+ MachineBasicBlock::iterator predMI = prior(BBI);
+ if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
// This instruction is in a delay slot of its predecessor, so
// replace it with a nop. By replacing in place, we save having
// to update the I-I maps.
//
assert(ndelay == 1 && "Not yet handling multiple-delay-slot targets");
- (*BBI)->replace(mii.getNOPOpCode(), 0);
+ BBI->replace(mii.getNOPOpCode(), 0);
return;
}
}
@@ -61,18 +62,17 @@
//----------------------------------------------------------------------------
static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
- if (MI->getOpCode() == V9::FMOVS || MI->getOpCode() == V9::FMOVD) {
+ if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
return (// both operands are allocated to the same register
- MI->getOperand(0).getAllocatedRegNum() ==
- MI->getOperand(1).getAllocatedRegNum());
- } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr ||
- MI->getOpCode() == V9::ADDi || MI->getOpCode() == V9::ORi) {
+ MI->getOperand(0).getReg() == MI->getOperand(1).getReg());
+ } else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
+ MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
- MI->getOperand(srcWithDestReg).getAllocatedRegNum()
- == MI->getOperand(2).getAllocatedRegNum())
+ MI->getOperand(srcWithDestReg).getReg()
+ == MI->getOperand(2).getReg())
break;
if (srcWithDestReg == 2)
@@ -82,7 +82,7 @@
unsigned otherOp = 1 - srcWithDestReg;
return (// either operand otherOp is register %g0
(MI->getOperand(otherOp).hasAllocatedReg() &&
- MI->getOperand(otherOp).getAllocatedRegNum() ==
+ MI->getOperand(otherOp).getReg() ==
target.getRegInfo().getZeroRegNum()) ||
// or operand otherOp == 0
@@ -99,7 +99,7 @@
RemoveUselessCopies(MachineBasicBlock& mvec,
MachineBasicBlock::iterator& BBI,
const TargetMachine& target) {
- if (IsUselessCopy(target, *BBI)) {
+ if (IsUselessCopy(target, BBI)) {
DeleteInstruction(mvec, BBI, target);
return true;
}
@@ -148,16 +148,8 @@
assert(MBB && "MachineBasicBlock object not found for specified block!");
MachineBasicBlock &mvec = *MBB;
- // Iterate over all machine instructions in the BB
- // Use a reverse iterator to allow deletion of MI or any instruction after it.
- // Insertions or deletions *before* MI are not safe.
- //
- for (MachineBasicBlock::reverse_iterator RI=mvec.rbegin(),
- RE=mvec.rend(); RI != RE; ) {
- MachineBasicBlock::iterator BBI = RI.base()-1; // save before incr
- ++RI; // pre-increment to delete MI or after it
- visit(mvec, BBI);
- }
+ for (MachineBasicBlock::iterator I = mvec.begin(), E = mvec.end(); I != E; )
+ visit(mvec, I++);
return true;
}
Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.27 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.27.2.1
--- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.27 Wed Dec 17 16:06:08 2003
+++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Mon Mar 1 17:58:15 2004
@@ -15,7 +15,7 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/iMemory.h"
Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.32 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.32.4.1
--- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.32 Wed Nov 12 18:18:04 2003
+++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Mon Mar 1 17:58:15 2004
@@ -16,8 +16,8 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
-#include "SparcRegClassInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegClassInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
@@ -31,7 +31,7 @@
namespace {
struct InsertPrologEpilogCode : public MachineFunctionPass {
- const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
+ const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; }
bool runOnMachineFunction(MachineFunction &F) {
if (!F.getInfo()->isCompiledAsLeafMethod()) {
@@ -74,7 +74,7 @@
int SP = TM.getRegInfo().getStackPointer();
if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
- .addMReg(SP, MOTy::Def));
+ .addMReg(SP, MachineOperand::Def));
} else {
// We have to put the stack size value into a register before SAVE.
// Use register %g1 since it is volatile across calls. Note that the
@@ -83,24 +83,25 @@
// SETSW -(stackSize), %g1
int uregNum = TM.getRegInfo().getUnifiedRegNum(
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
- SparcIntRegClass::g1);
+ SparcV9IntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
- .addMReg(uregNum, MOTy::Def);
+ .addMReg(uregNum, MachineOperand::Def);
M->setOperandHi32(0);
mvec.push_back(M);
M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
- .addMReg(uregNum, MOTy::Def);
+ .addMReg(uregNum, MachineOperand::Def);
M->setOperandLo32(1);
mvec.push_back(M);
M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
- .addMReg(uregNum, MOTy::Def);
+ .addMReg(uregNum, MachineOperand::Def);
mvec.push_back(M);
// Now generate the SAVE using the value in register %g1
- M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
+ M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
+ .addMReg(SP,MachineOperand::Def);
mvec.push_back(M);
}
@@ -118,7 +119,7 @@
bool ignore;
int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
- SparcIntRegClass::i0);
+ SparcV9IntRegClass::i0);
int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);
@@ -148,25 +149,26 @@
{
int ZR = TM.getRegInfo().getZeroRegNum();
MachineInstr *Restore =
- BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
+ BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
+ .addMReg(ZR, MachineOperand::Def);
MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst);
// Remove the NOPs in the delay slots of the return instruction
unsigned numNOPs = 0;
- while (termMvec.back()->getOpCode() == V9::NOP)
+ while (termMvec.back()->getOpcode() == V9::NOP)
{
- assert( termMvec.back() == MBB.back());
- delete MBB.pop_back();
+ assert( termMvec.back() == &MBB.back());
termMvec.pop_back();
+ MBB.erase(&MBB.back());
++numNOPs;
}
- assert(termMvec.back() == MBB.back());
+ assert(termMvec.back() == &MBB.back());
// Check that we found the right number of NOPs and have the right
// number of instructions to replace them.
- unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode());
+ unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.34 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.34.2.1
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.34 Fri Jan 9 10:17:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcRegClassInfo.cpp - Register class def'ns for Sparc -----------===//
+//===-- SparcV9RegClassInfo.cpp - Register class def'ns for SparcV9 -----------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,14 +7,14 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines the register classes used by the Sparc target description.
+// This file defines the register classes used by the SparcV9 target description.
//
//===----------------------------------------------------------------------===//
#include "llvm/Type.h"
-#include "SparcRegClassInfo.h"
-#include "SparcInternals.h"
-#include "SparcRegInfo.h"
+#include "SparcV9RegClassInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegInfo.h"
#include "RegAlloc/RegAllocCommon.h"
#include "RegAlloc/IGNode.h"
@@ -33,7 +33,7 @@
// If both above fail, spill.
//
//-----------------------------------------------------------------------------
-void SparcIntRegClass::colorIGNode(IGNode * Node,
+void SparcV9IntRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
{
LiveRange *LR = Node->getParentLR();
@@ -69,16 +69,16 @@
//if this Node is between calls
if (! LR->isCallInterference()) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcIntRegClass::StartOfAllRegs;
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcIntRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
}
unsigned c=0; // color
// find first unused color
- for (c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) {
+ for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
if (!IsColorUsedArr[c]) {
ColorFound = true;
break;
@@ -95,10 +95,10 @@
//
else if (LR->isCallInterference()) {
// start from 0 - try to find even a volatile this time
- SearchStart = SparcIntRegClass::StartOfAllRegs;
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
// find first unused volatile color
- for(c=SearchStart; c < SparcIntRegClass::StartOfNonVolatileRegs; c++) {
+ for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
if (! IsColorUsedArr[c]) {
ColorFound = true;
break;
@@ -140,7 +140,7 @@
// Note: The third name (%ccr) is essentially an assembly mnemonic and
// depends solely on the opcode, so the name can be chosen in EmitAssembly.
//-----------------------------------------------------------------------------
-void SparcIntCCRegClass::colorIGNode(IGNode *Node,
+void SparcV9IntCCRegClass::colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const
{
if (Node->getNumOfNeighbors() > 0)
@@ -173,7 +173,7 @@
}
-void SparcFloatCCRegClass::colorIGNode(IGNode *Node,
+void SparcV9FloatCCRegClass::colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
if (!IsColorUsedArr[c]) { // find unused color
@@ -201,7 +201,7 @@
// If a color is still not fond, mark for spilling
//
//----------------------------------------------------------------------------
-void SparcFloatRegClass::colorIGNode(IGNode * Node,
+void SparcV9FloatRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
{
LiveRange *LR = Node->getParentLR();
@@ -211,11 +211,11 @@
//
// FIXME: This is old code that is no longer needed. Temporarily converting
// it into a big assertion just to check that the replacement logic
- // (invoking SparcFloatRegClass::markColorsUsed() directly from
+ // (invoking SparcV9FloatRegClass::markColorsUsed() directly from
// RegClass::colorIGNode) works correctly.
//
// In fact, this entire function should be identical to
- // SparcIntRegClass::colorIGNode(), and perhaps can be
+ // SparcV9IntRegClass::colorIGNode(), and perhaps can be
// made into a general case in CodeGen/RegAlloc/RegClass.cpp.
//
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
@@ -242,7 +242,7 @@
// **NOTE: We don't check for call interferences in allocating suggested
// color in this class since ALL registers are volatile. If this fact
// changes, we should change the following part
- //- see SparcIntRegClass::colorIGNode()
+ //- see SparcV9IntRegClass::colorIGNode()
//
if( LR->hasSuggestedColor() ) {
if( ! IsColorUsedArr[ LR->getSuggestedColor() ] ) {
@@ -280,10 +280,10 @@
//if this Node is between calls (i.e., no call interferences )
if (! isCallInterf) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcFloatRegClass::StartOfAllRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcFloatRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
}
ColorFound = findFloatColor(LR, SearchStart, 32, IsColorUsedArr);
@@ -296,8 +296,8 @@
// We are here because there is a call interference and no non-volatile
// color could be found.
// Now try to allocate even a volatile color
- ColorFound = findFloatColor(LR, SparcFloatRegClass::StartOfAllRegs,
- SparcFloatRegClass::StartOfNonVolatileRegs,
+ ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
+ SparcV9FloatRegClass::StartOfNonVolatileRegs,
IsColorUsedArr);
}
@@ -316,13 +316,13 @@
// for double-precision registers.
//-----------------------------------------------------------------------------
-void SparcFloatRegClass::markColorsUsed(unsigned RegInClass,
+void SparcV9FloatRegClass::markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
std::vector<bool> &IsColorUsedArr) const
{
- if (UserRegType == SparcRegInfo::FPDoubleRegType ||
- RegTypeWanted == SparcRegInfo::FPDoubleRegType) {
+ if (UserRegType == SparcV9RegInfo::FPDoubleRegType ||
+ RegTypeWanted == SparcV9RegInfo::FPDoubleRegType) {
// This register is used as or is needed as a double-precision reg.
// We need to mark the [even,odd] pair corresponding to this reg.
// Get the even numbered register corresponding to this reg.
@@ -346,10 +346,10 @@
// for double-precision registers
// It returns -1 if no unused color is found.
//
-int SparcFloatRegClass::findUnusedColor(int RegTypeWanted,
+int SparcV9FloatRegClass::findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const
{
- if (RegTypeWanted == SparcRegInfo::FPDoubleRegType) {
+ if (RegTypeWanted == SparcV9RegInfo::FPDoubleRegType) {
unsigned NC = 2 * this->getNumOfAvailRegs();
assert(IsColorUsedArr.size() == NC && "Invalid colors-used array");
for (unsigned c = 0; c < NC; c+=2)
@@ -369,7 +369,7 @@
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
+int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
unsigned Start,
unsigned End,
const std::vector<bool> &IsColorUsedArr) const
@@ -380,7 +380,7 @@
for (unsigned c=Start; c < End ; c+= 2)
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] &&
- "Incorrect marking of used regs for Sparc FP double!");
+ "Incorrect marking of used regs for SparcV9 FP double!");
return c;
}
} else {
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.23 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.23.4.1
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.23 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcRegClassInfo.h - Register class def'ns for Sparc ---*- C++ -*-===//
+//===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines the register classes used by the Sparc target description.
+// This file defines the register classes used by the SparcV9 target description.
//
//===----------------------------------------------------------------------===//
@@ -22,8 +22,8 @@
// Integer Register Class
//-----------------------------------------------------------------------------
-struct SparcIntRegClass : public TargetRegClassInfo {
- SparcIntRegClass(unsigned ID)
+struct SparcV9IntRegClass : public TargetRegClassInfo {
+ SparcV9IntRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node,
@@ -87,12 +87,12 @@
// Float Register Class
//-----------------------------------------------------------------------------
-class SparcFloatRegClass : public TargetRegClassInfo {
+class SparcV9FloatRegClass : public TargetRegClassInfo {
int findFloatColor(const LiveRange *LR, unsigned Start,
unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
- SparcFloatRegClass(unsigned ID)
+ SparcV9FloatRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
// This method marks the registers used for a given register number.
@@ -116,7 +116,7 @@
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
- // according to Sparc 64 ABI, all %fp regs are volatile
+ // according to SparcV9 64 ABI, all %fp regs are volatile
inline bool isRegVolatile(int Reg) const { return true; }
enum {
@@ -153,14 +153,14 @@
// allocated for the three names.
//-----------------------------------------------------------------------------
-struct SparcIntCCRegClass : public TargetRegClassInfo {
- SparcIntCCRegClass(unsigned ID)
+struct SparcV9IntCCRegClass : public TargetRegClassInfo {
+ SparcV9IntCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 1, 3) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
- // according to Sparc 64 ABI, %ccr is volatile
+ // according to SparcV9 64 ABI, %ccr is volatile
//
inline bool isRegVolatile(int Reg) const { return true; }
@@ -177,14 +177,14 @@
// Only 4 Float CC registers are available for allocation.
//-----------------------------------------------------------------------------
-struct SparcFloatCCRegClass : public TargetRegClassInfo {
- SparcFloatCCRegClass(unsigned ID)
+struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
+ SparcV9FloatCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 4, 5) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
- // according to Sparc 64 ABI, all %fp CC regs are volatile
+ // according to SparcV9 64 ABI, all %fp CC regs are volatile
//
inline bool isRegVolatile(int Reg) const { return true; }
@@ -196,17 +196,17 @@
};
//-----------------------------------------------------------------------------
-// Sparc special register class. These registers are not used for allocation
+// SparcV9 special register class. These registers are not used for allocation
// but are used as arguments of some instructions.
//-----------------------------------------------------------------------------
-struct SparcSpecialRegClass : public TargetRegClassInfo {
- SparcSpecialRegClass(unsigned ID)
+struct SparcV9SpecialRegClass : public TargetRegClassInfo {
+ SparcV9SpecialRegClass(unsigned ID)
: TargetRegClassInfo(ID, 0, 1) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
- assert(0 && "SparcSpecialRegClass should never be used for allocation");
+ assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
}
// all currently included special regs are volatile
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.116 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.116.2.1
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.116 Fri Jan 9 10:17:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
+//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information --------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains implementation of Sparc specific helper methods
+// This file contains implementation of SparcV9 specific helper methods
// used for register allocation.
//
//===----------------------------------------------------------------------===//
@@ -17,17 +17,17 @@
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineInstrAnnot.h"
+#include "MachineInstrAnnot.h"
#include "RegAlloc/LiveRangeInfo.h"
#include "RegAlloc/LiveRange.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/iTerminators.h"
#include "llvm/iOther.h"
-#include "SparcInternals.h"
-#include "SparcRegClassInfo.h"
-#include "SparcRegInfo.h"
-#include "SparcTargetMachine.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegClassInfo.h"
+#include "SparcV9RegInfo.h"
+#include "SparcV9TargetMachine.h"
namespace llvm {
@@ -35,16 +35,16 @@
BadRegClass = ~0
};
-SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
+SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
: TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
{
- MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
- MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
- MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
- MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
- MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
+ MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
+ MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
+ MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
+ MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
+ MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
- assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
+ assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
@@ -52,31 +52,31 @@
// getZeroRegNum - returns the register that contains always zero.
// this is the unified register number
//
-int SparcRegInfo::getZeroRegNum() const {
- return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::g0);
+unsigned SparcV9RegInfo::getZeroRegNum() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::g0);
}
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
-unsigned SparcRegInfo::getCallAddressReg() const {
- return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::o7);
+unsigned SparcV9RegInfo::getCallAddressReg() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::o7);
}
// Returns the register containing the return address.
// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
-unsigned SparcRegInfo::getReturnAddressReg() const {
- return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::i7);
+unsigned SparcV9RegInfo::getReturnAddressReg() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::i7);
}
// Register get name implementations...
-// Int register names in same order as enum in class SparcIntRegClass
+// Int register names in same order as enum in class SparcV9IntRegClass
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
@@ -86,7 +86,7 @@
"o6"
};
-const char * const SparcIntRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
@@ -101,7 +101,7 @@
"f60", "f61", "f62", "f63"
};
-const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
assert (reg < NumOfAllRegs);
return FloatRegNames[reg];
}
@@ -111,7 +111,7 @@
"xcc", "icc", "ccr"
};
-const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
assert(reg < 3);
return IntCCRegNames[reg];
}
@@ -120,7 +120,7 @@
"fcc0", "fcc1", "fcc2", "fcc3"
};
-const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
assert (reg < 5);
return FloatCCRegNames[reg];
}
@@ -129,21 +129,21 @@
"fsr"
};
-const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
assert (reg < 1);
return SpecialRegNames[reg];
}
// Get unified reg number for frame pointer
-unsigned SparcRegInfo::getFramePointer() const {
- return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::i6);
+unsigned SparcV9RegInfo::getFramePointer() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::i6);
}
// Get unified reg number for stack pointer
-unsigned SparcRegInfo::getStackPointer() const {
- return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::o6);
+unsigned SparcV9RegInfo::getStackPointer() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::o6);
}
@@ -175,14 +175,14 @@
// regClassId is set to the register class ID.
//
int
-SparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
+SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
regClassId = IntRegClassID;
if (argNo >= NumOfIntArgRegs)
return getInvalidRegNum();
else
- return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
+ return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
}
// Get the register number for the specified FP argument #argNo,
@@ -194,7 +194,7 @@
// regClassId is set to the register class ID.
//
int
-SparcRegInfo::regNumForFPArg(unsigned regType,
+SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
@@ -205,10 +205,10 @@
regClassId = FloatRegClassID;
if (regType == FPSingleRegType)
return (argNo*2+1 >= NumOfFloatArgRegs)?
- getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
+ getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
else if (regType == FPDoubleRegType)
return (argNo*2 >= NumOfFloatArgRegs)?
- getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
+ getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
return 0;
@@ -220,10 +220,10 @@
// Finds the return address of a call sparc specific call instruction
//---------------------------------------------------------------------------
-// The following 4 methods are used to find the RegType (SparcInternals.h)
+// The following 4 methods are used to find the RegType (SparcV9Internals.h)
// of a LiveRange, a Value, and for a given register unified reg number.
//
-int SparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
+int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
const Type* type) const
{
switch (regClassID) {
@@ -239,17 +239,17 @@
}
}
-int SparcRegInfo::getRegTypeForDataType(const Type* type) const
+int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
{
return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
}
-int SparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
+int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
{
return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
}
-int SparcRegInfo::getRegType(int unifiedRegNum) const
+int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
if (unifiedRegNum < 32)
return IntRegType;
@@ -269,7 +269,7 @@
// To find the register class used for a specified Type
//
-unsigned SparcRegInfo::getRegClassIDOfType(const Type *type,
+unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
bool isCCReg) const {
Type::PrimitiveID ty = type->getPrimitiveID();
unsigned res;
@@ -292,7 +292,7 @@
return res;
}
-unsigned SparcRegInfo::getRegClassIDOfRegType(int regType) const {
+unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
switch(regType) {
case IntRegType: return IntRegClassID;
case FPSingleRegType:
@@ -309,14 +309,14 @@
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void SparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
+ assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
- SparcIntRegClass::i7));
+ SparcV9IntRegClass::i7));
// Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
@@ -329,16 +329,16 @@
// assert( RetAddrVal && "LR for ret address must be created at start");
// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
- // SparcIntRegOrdr::i7) );
+ // SparcV9IntRegOrdr::i7) );
}
//---------------------------------------------------------------------------
// Suggests a register for the ret address in the JMPL/CALL machine instr.
-// Sparc ABI dictates that %o7 be used for this purpose.
+// SparcV9 ABI dictates that %o7 be used for this purpose.
//---------------------------------------------------------------------------
void
-SparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
+SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@@ -350,19 +350,19 @@
assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
unsigned RegClassID = RetAddrLR->getRegClassID();
- RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
+ RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
}
//---------------------------------------------------------------------------
// This method will suggest colors to incoming args to a method.
-// According to the Sparc ABI, the first 6 incoming args are in
+// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
-void SparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
+void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
@@ -395,7 +395,7 @@
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
-void SparcRegInfo::colorMethodArgs(const Function *Meth,
+void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
@@ -568,9 +568,9 @@
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
- assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@@ -588,9 +588,9 @@
// now suggest a register depending on the register class of ret arg
if( RegClassID == IntRegClassID )
- RetValLR->setSuggestedColor(SparcIntRegClass::o0);
+ RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
else if (RegClassID == FloatRegClassID )
- RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
+ RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
@@ -636,10 +636,10 @@
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
suggestReg4RetAddr(RetMI, LRI);
@@ -650,8 +650,8 @@
if (const Value *RetVal = retI->getReturnValue())
if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
- ? (unsigned) SparcIntRegClass::i0
- : (unsigned) SparcFloatRegClass::f0);
+ ? (unsigned) SparcV9IntRegClass::i0
+ : (unsigned) SparcV9FloatRegClass::f0);
}
//---------------------------------------------------------------------------
@@ -664,7 +664,7 @@
//---------------------------------------------------------------------------
bool
-SparcRegInfo::regTypeNeedsScratchReg(int RegType,
+SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
int& scratchRegType) const
{
if (RegType == IntCCRegType)
@@ -681,7 +681,7 @@
//---------------------------------------------------------------------------
void
-SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
+SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
@@ -697,18 +697,19 @@
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
MI = (BuildMI(V9::RDCCR, 2)
- .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr))
- .addMReg(DestReg,MOTy::Def));
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr))
+ .addMReg(DestReg,MachineOperand::Def));
} else {
// copy int reg to intCC reg
assert(getRegType(SrcReg) == IntRegType
&& "Can only copy CC reg to/from integer reg");
MI = (BuildMI(V9::WRCCRr, 3)
.addMReg(SrcReg)
- .addMReg(SparcIntRegClass::g0)
- .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr), MOTy::Def));
+ .addMReg(SparcV9IntRegClass::g0)
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr),
+ MachineOperand::Def));
}
break;
@@ -718,15 +719,17 @@
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
- .addMReg(DestReg, MOTy::Def);
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
- MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+ MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
- MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+ MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
default:
@@ -745,7 +748,7 @@
void
-SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
+SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned PtrReg,
int Offset, int RegType,
@@ -765,8 +768,8 @@
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g4 for holding large offsets
- OffReg = getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::g4);
+ OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::g4);
#endif
assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
@@ -798,17 +801,17 @@
assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
MI = (BuildMI(V9::RDCCR, 2)
- .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr))
- .addMReg(scratchReg, MOTy::Def));
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr))
+ .addMReg(scratchReg, MachineOperand::Def));
mvec.push_back(MI);
cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
return;
case FloatCCRegType: {
- unsigned fsrReg = getUnifiedRegNum(SparcRegInfo::SpecialRegClassID,
- SparcSpecialRegClass::fsr);
+ unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
+ SparcV9SpecialRegClass::fsr);
if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
else
@@ -829,7 +832,7 @@
void
-SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
+SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
unsigned PtrReg,
int Offset,
unsigned DestReg,
@@ -850,8 +853,8 @@
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g4 for holding large offsets
- OffReg = getUnifiedRegNum(SparcRegInfo::IntRegClassID,
- SparcIntRegClass::g4);
+ OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::g4);
#endif
assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
@@ -860,29 +863,29 @@
switch (RegType) {
case IntRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
- MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
- MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
- MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case IntCCRegType:
@@ -891,20 +894,20 @@
cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
MI = (BuildMI(V9::WRCCRr, 3)
.addMReg(scratchReg)
- .addMReg(SparcIntRegClass::g0)
- .addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr), MOTy::Def));
+ .addMReg(SparcV9IntRegClass::g0)
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr), MachineOperand::Def));
break;
case FloatCCRegType: {
- unsigned fsrRegNum = getUnifiedRegNum(SparcRegInfo::SpecialRegClassID,
- SparcSpecialRegClass::fsr);
+ unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
+ SparcV9SpecialRegClass::fsr);
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
- .addMReg(fsrRegNum, MOTy::UseAndDef);
+ .addMReg(fsrRegNum, MachineOperand::UseAndDef);
else
MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
- .addMReg(fsrRegNum, MOTy::UseAndDef);
+ .addMReg(fsrRegNum, MachineOperand::UseAndDef);
break;
}
default:
@@ -921,7 +924,7 @@
void
-SparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
+SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
std::vector<MachineInstr*>& mvec) const {
int RegType = getRegTypeForDataType(Src->getType());
MachineInstr * MI = NULL;
@@ -950,7 +953,7 @@
// Print the register assigned to a LR
//---------------------------------------------------------------------------
-void SparcRegInfo::printReg(const LiveRange *LR) const {
+void SparcV9RegInfo::printReg(const LiveRange *LR) const {
unsigned RegClassID = LR->getRegClassID();
std::cerr << " Node ";
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.8 llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.8.2.1
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.8 Thu Jan 15 12:17:07 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcRegInfo.h - Define TargetRegInfo for Sparc ---------*- C++ -*-===//
+//===-- SparcV9RegInfo.h - Define TargetRegInfo for SparcV9 ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This class implements the virtual class TargetRegInfo for Sparc.
+// This class implements the virtual class TargetRegInfo for SparcV9.
//
//----------------------------------------------------------------------------
@@ -18,9 +18,9 @@
namespace llvm {
-class SparcTargetMachine;
+class SparcV9TargetMachine;
-class SparcRegInfo : public TargetRegInfo {
+class SparcV9RegInfo : public TargetRegInfo {
private:
@@ -34,7 +34,7 @@
// The following methods are used to color special live ranges (e.g.
// function args and return values etc.) with specific hardware registers
- // as required. See SparcRegInfo.cpp for the implementation.
+ // as required. See SparcV9RegInfo.cpp for the implementation.
//
void suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo &LRI) const;
@@ -45,7 +45,7 @@
int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
public:
- // Type of registers available in Sparc. There can be several reg types
+ // Type of registers available in SparcV9. There can be several reg types
// in the same class. For instace, the float reg class has Single/Double
// types
//
@@ -58,7 +58,7 @@
SpecialRegType
};
- // The actual register classes in the Sparc
+ // The actual register classes in the SparcV9
//
// **** WARNING: If this enum order is changed, also modify
// getRegisterClassOfValue method below since it assumes this particular
@@ -72,7 +72,7 @@
SpecialRegClassID // Special (unallocated) registers
};
- SparcRegInfo(const SparcTargetMachine &tgt);
+ SparcV9RegInfo(const SparcV9TargetMachine &tgt);
// To find the register class used for a specified Type
//
@@ -86,7 +86,7 @@
// getZeroRegNum - returns the register that contains always zero this is the
// unified register number
//
- virtual int getZeroRegNum() const;
+ virtual unsigned getZeroRegNum() const;
// getCallAddressReg - returns the reg used for pushing the address when a
// function is called. This can be used for other purposes between calls
@@ -115,7 +115,7 @@
// The following methods are used to color special live ranges (e.g.
// function args and return values etc.) with specific hardware registers
- // as required. See SparcRegInfo.cpp for the implementation for Sparc.
+ // as required. See SparcV9RegInfo.cpp for the implementation for SparcV9.
//
void suggestRegs4MethodArgs(const Function *Meth,
LiveRangeInfo& LRI) const;
@@ -135,7 +135,7 @@
void printReg(const LiveRange *LR) const;
// returns the # of bytes of stack space allocated for each register
- // type. For Sparc, currently we allocate 8 bytes on stack for all
+ // type. For SparcV9, currently we allocate 8 bytes on stack for all
// register types. We can optimize this later if necessary to save stack
// space (However, should make sure that stack alignment is correct)
//
Index: llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.9 llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.9.2.1
--- llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.9 Wed Dec 17 16:04:00 2003
+++ llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- UltraSparcSchedInfo.cpp -------------------------------------------===//
+//===-- UltraSparcV9SchedInfo.cpp -------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
-// Describe the scheduling characteristics of the UltraSparc
+// Describe the scheduling characteristics of the UltraSparcV9
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
using namespace llvm;
@@ -129,7 +129,7 @@
//---------------------------------------------------------------------------
-// const InstrClassRUsage SparcRUsageDesc[]
+// const InstrClassRUsage SparcV9RUsageDesc[]
//
// Purpose:
// Resource usage information for instruction in each scheduling class.
@@ -396,7 +396,7 @@
};
-static const InstrClassRUsage SparcRUsageDesc[] = {
+static const InstrClassRUsage SparcV9RUsageDesc[] = {
NoneClassRUsage,
IEUNClassRUsage,
IEU0ClassRUsage,
@@ -412,14 +412,14 @@
//---------------------------------------------------------------------------
-// const InstrIssueDelta SparcInstrIssueDeltas[]
+// const InstrIssueDelta SparcV9InstrIssueDeltas[]
//
// Purpose:
// Changes to issue restrictions information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
//---------------------------------------------------------------------------
-static const InstrIssueDelta SparcInstrIssueDeltas[] = {
+static const InstrIssueDelta SparcV9InstrIssueDeltas[] = {
// opCode, isSingleIssue, breaksGroup, numBubbles
@@ -504,14 +504,14 @@
//---------------------------------------------------------------------------
-// const InstrRUsageDelta SparcInstrUsageDeltas[]
+// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
//
// Purpose:
// Changes to resource usage information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
//---------------------------------------------------------------------------
-static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
+static const InstrRUsageDelta SparcV9InstrUsageDeltas[] = {
// MachineOpCode, Resource, Start cycle, Num cycles
@@ -601,7 +601,7 @@
#ifdef EXPLICIT_BUBBLES_NEEDED
//
// MULScc inserts one bubble.
- // This means it breaks the current group (captured in UltraSparcSchedInfo)
+ // This means it breaks the current group (captured in UltraSparcV9SchedInfo)
// *and occupies all issue slots for the next cycle
//
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
@@ -728,7 +728,7 @@
//---------------------------------------------------------------------------
-// class SparcSchedInfo
+// class SparcV9SchedInfo
//
// Purpose:
// Scheduling information for the UltraSPARC.
@@ -737,34 +737,24 @@
//---------------------------------------------------------------------------
/*ctor*/
-SparcSchedInfo::SparcSchedInfo(const TargetMachine& tgt)
+SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
: TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
- SparcRUsageDesc,
- SparcInstrUsageDeltas,
- SparcInstrIssueDeltas,
- sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
+ SparcV9RUsageDesc,
+ SparcV9InstrUsageDeltas,
+ SparcV9InstrIssueDeltas,
+ sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
+ sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
longestIssueConflict = 0; // computed from issuesGaps[]
- branchMispredictPenalty = 4; // 4 for SPARC IIi
- branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
- l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
- l1ICacheMissPenalty = 8; // ? for SPARC IIi
-
- inOrderLoads = true; // true for SPARC IIi
- inOrderIssue = true; // true for SPARC IIi
- inOrderExec = false; // false for most architectures
- inOrderRetire= true; // true for most architectures
-
// must be called after above parameters are initialized.
initializeResources();
}
void
-SparcSchedInfo::initializeResources()
+SparcV9SchedInfo::initializeResources()
{
// Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
TargetSchedInfo::initializeResources();
Index: llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.9 llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.9.4.1
--- llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.9 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp Mon Mar 1 17:58:15 2004
@@ -13,7 +13,7 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.98 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.98.2.1
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.98 Tue Jan 13 13:26:21 2004
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
+//===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
//
// The LLVM Compiler Infrastructure
//
@@ -26,21 +26,21 @@
#include "llvm/Target/TargetMachineImpls.h"
#include "llvm/Transforms/Scalar.h"
#include "MappingInfo.h"
-#include "SparcInternals.h"
-#include "SparcTargetMachine.h"
+#include "SparcV9Internals.h"
+#include "SparcV9TargetMachine.h"
#include "Support/CommandLine.h"
using namespace llvm;
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
-const TargetInstrDescriptor llvm::SparcMachineInstrDesc[] = {
+const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
ImplicitRegUseList, ImplicitRegUseList },
-#include "SparcInstr.def"
+#include "SparcV9Instr.def"
};
//---------------------------------------------------------------------------
@@ -82,7 +82,7 @@
};
struct DestroyMachineFunction : public FunctionPass {
- const char *getPassName() const { return "FreeMachineFunction"; }
+ const char *getPassName() const { return "DestroyMachineFunction"; }
static void freeMachineCode(Instruction &I) {
MachineCodeForInstruction::destroy(&I);
@@ -106,25 +106,24 @@
}
}
-FunctionPass *llvm::createSparcMachineCodeDestructionPass() {
+FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
return new DestroyMachineFunction();
}
-SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
- : TargetMachine("UltraSparc-Native", il, false),
+SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
+ : TargetMachine("UltraSparcV9-Native", il, false),
schedInfo(*this),
regInfo(*this),
frameInfo(*this),
- cacheInfo(*this),
jitInfo(*this) {
}
-// addPassesToEmitAssembly - This method controls the entire code generation
-// process for the ultra sparc.
-//
+/// addPassesToEmitAssembly - This method controls the entire code generation
+/// process for the ultra sparc.
+///
bool
-SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
+SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
{
// The following 3 passes used to be inserted specially by llc.
// Replace malloc and free instructions with library calls.
@@ -176,9 +175,10 @@
// function output is pipelined with all of the rest of code generation stuff,
// allowing machine code representations for functions to be free'd after the
// function has been emitted.
- //
PM.add(createAsmPrinterPass(Out, *this));
- PM.add(createSparcMachineCodeDestructionPass()); // Free mem no longer needed
+
+ // Free machine-code IR which is no longer needed:
+ PM.add(createSparcV9MachineCodeDestructionPass());
// Emit bytecode to the assembly file into its special section next
if (EmitMappingInfo)
@@ -187,10 +187,10 @@
return false;
}
-// addPassesToJITCompile - This method controls the JIT method of code
-// generation for the UltraSparc.
-//
-void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+/// addPassesToJITCompile - This method controls the JIT method of code
+/// generation for the UltraSparcV9.
+///
+void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
const TargetData &TD = TM.getTargetData();
PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
@@ -230,12 +230,10 @@
PM.add(createPeepholeOptsPass(TM));
}
-//----------------------------------------------------------------------------
-// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
-// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
-//----------------------------------------------------------------------------
-
-TargetMachine *llvm::allocateSparcTargetMachine(const Module &M,
+/// allocateSparcV9TargetMachine - Allocate and return a subclass of TargetMachine
+/// that implements the SparcV9 backend. (the llvm/CodeGen/SparcV9.h interface)
+///
+TargetMachine *llvm::allocateSparcV9TargetMachine(const Module &M,
IntrinsicLowering *IL) {
- return new SparcTargetMachine(IL);
+ return new SparcV9TargetMachine(IL);
}
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.h
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.4 llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.4.2.1
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.4 Sun Dec 28 15:23:38 2003
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.h Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
+//===-- SparcV9TargetMachine.h - Define TargetMachine for SparcV9 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,30 +16,28 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "SparcInstrInfo.h"
-#include "SparcInternals.h"
-#include "SparcRegInfo.h"
-#include "SparcFrameInfo.h"
-#include "SparcJITInfo.h"
+#include "SparcV9InstrInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegInfo.h"
+#include "SparcV9FrameInfo.h"
+#include "SparcV9JITInfo.h"
namespace llvm {
class PassManager;
-class SparcTargetMachine : public TargetMachine {
- SparcInstrInfo instrInfo;
- SparcSchedInfo schedInfo;
- SparcRegInfo regInfo;
- SparcFrameInfo frameInfo;
- SparcCacheInfo cacheInfo;
- SparcJITInfo jitInfo;
+class SparcV9TargetMachine : public TargetMachine {
+ SparcV9InstrInfo instrInfo;
+ SparcV9SchedInfo schedInfo;
+ SparcV9RegInfo regInfo;
+ SparcV9FrameInfo frameInfo;
+ SparcV9JITInfo jitInfo;
public:
- SparcTargetMachine(IntrinsicLowering *IL);
+ SparcV9TargetMachine(IntrinsicLowering *IL);
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
- virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
virtual TargetJITInfo *getJITInfo() { return &jitInfo; }
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
Index: llvm/lib/Target/SparcV9/SparcV9_F2.td
diff -u llvm/lib/Target/SparcV9/SparcV9_F2.td:1.8 llvm/lib/Target/SparcV9/SparcV9_F2.td:1.8.6.1
--- llvm/lib/Target/SparcV9/SparcV9_F2.td:1.8 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/SparcV9/SparcV9_F2.td Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===- SparcV9_F2.td - Format 2 instructions: Sparc V9 Target -------------===//
+//===- SparcV9_F2.td - Format 2 instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -32,7 +32,7 @@
class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
bits<22> disp;
- bit annul = 0; // currently unused by Sparc backend
+ bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;
@@ -44,7 +44,7 @@
bits<2> cc;
bits<19> disp;
bit predict = 1;
- bit annul = 0; // currently unused by Sparc backend
+ bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;
@@ -58,7 +58,7 @@
bits<5> rs1;
bits<16> disp;
bit predict = 1;
- bit annul = 0; // currently unused by Sparc backend
+ bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;
Index: llvm/lib/Target/SparcV9/SparcV9_F3.td
diff -u llvm/lib/Target/SparcV9/SparcV9_F3.td:1.17 llvm/lib/Target/SparcV9/SparcV9_F3.td:1.17.6.1
--- llvm/lib/Target/SparcV9/SparcV9_F3.td:1.17 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/SparcV9/SparcV9_F3.td Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===- SparcV9_F3.td - Format 3 Instructions: Sparc V9 Target -------------===//
+//===- SparcV9_F3.td - Format 3 Instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//
Index: llvm/lib/Target/SparcV9/SparcV9_F4.td
diff -u llvm/lib/Target/SparcV9/SparcV9_F4.td:1.10 llvm/lib/Target/SparcV9/SparcV9_F4.td:1.10.6.1
--- llvm/lib/Target/SparcV9/SparcV9_F4.td:1.10 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/SparcV9/SparcV9_F4.td Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===- SparcV9_F4.td - Format 4 instructions: Sparc V9 Target -------------===//
+//===- SparcV9_F4.td - Format 4 instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//
Index: llvm/lib/Target/SparcV9/SparcV9_Reg.td
diff -u llvm/lib/Target/SparcV9/SparcV9_Reg.td:1.7 llvm/lib/Target/SparcV9/SparcV9_Reg.td:1.7.4.1
--- llvm/lib/Target/SparcV9/SparcV9_Reg.td:1.7 Sat Nov 8 12:12:24 2003
+++ llvm/lib/Target/SparcV9/SparcV9_Reg.td Mon Mar 1 17:58:15 2004
@@ -1,4 +1,4 @@
-//===- SparcV9_Reg.td - Sparc V9 Register definitions ---------------------===//
+//===- SparcV9_Reg.td - SparcV9 V9 Register definitions ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// Declarations that describe the Sparc register file
+// Declarations that describe the SparcV9 register file
//===----------------------------------------------------------------------===//
// Ri - One of the 32 64 bit integer registers
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