[llvm-commits] [parallel] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedGraph.h SchedPriorities.cpp
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:04:14 PST 2004
Changes in directory llvm/lib/CodeGen/InstrSched:
InstrScheduling.cpp updated: 1.62 -> 1.62.4.1
SchedGraph.cpp updated: 1.54 -> 1.54.2.1
SchedGraph.h updated: 1.38 -> 1.38.2.1
SchedPriorities.cpp updated: 1.29 -> 1.29.4.1
---
Log message:
Merge from trunk
---
Diffs of the changes: (+113 -140)
Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.62 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.62.4.1
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.62 Tue Nov 11 16:41:32 2003
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Mon Mar 1 17:58:13 2004
@@ -16,7 +16,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/FunctionLiveVarInfo.h"
+#include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
#include "Support/CommandLine.h"
@@ -149,10 +149,10 @@
typedef ScheduleIterator<SchedGraphNode> iterator;
typedef ScheduleIterator<const SchedGraphNode> const_iterator;
- iterator begin();
- const_iterator begin() const;
- iterator end();
- const_iterator end() const;
+ iterator begin() { return iterator::begin(*this); }
+ const_iterator begin() const { return const_iterator::begin(*this); }
+ iterator end() { return iterator::end(*this); }
+ const_iterator end() const { return const_iterator::end(*this); }
public: // constructors and destructor
/*ctor*/ InstrSchedule (unsigned int _nslots,
@@ -280,30 +280,6 @@
return _Self(_schedule, _schedule.groups.size(), 0);
}
-InstrSchedule::iterator
-InstrSchedule::begin()
-{
- return iterator::begin(*this);
-}
-
-InstrSchedule::const_iterator
-InstrSchedule::begin() const
-{
- return const_iterator::begin(*this);
-}
-
-InstrSchedule::iterator
-InstrSchedule::end()
-{
- return iterator::end(*this);
-}
-
-InstrSchedule::const_iterator
-InstrSchedule::end() const
-{
- return const_iterator::end( *this);
-}
-
//----------------------------------------------------------------------
// class DelaySlotInfo:
@@ -448,7 +424,7 @@
// Append the instruction to the vector of choices for current cycle.
// Increment numInClass[c] for the sched class to which the instr belongs.
choiceVec.push_back(node);
- const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+ const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
assert(sc < numInClass.size());
numInClass[sc]++;
}
@@ -502,7 +478,7 @@
choicesForSlot[s].erase(node);
// and decrement the instr count for the sched class to which it belongs
- const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+ const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
assert(sc < numInClass.size());
numInClass[sc]--;
}
@@ -522,7 +498,7 @@
if (!createIfMissing) return 0;
DelaySlotInfo *dinfo =
- new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpCode()));
+ new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpcode()));
return delaySlotInfoForBranches[bn] = dinfo;
}
@@ -544,7 +520,7 @@
nextEarliestIssueTime(0),
choicesForSlot(nslots),
numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
- nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
+ nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(),
(cycles_t) 0) // set all to 0
{
updateTime(0);
@@ -561,19 +537,19 @@
SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
cycles_t schedTime)
{
- if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
+ if (schedInfo.numBubblesAfter(node->getOpcode()) > 0)
{ // Update next earliest time before which *nothing* can issue.
nextEarliestIssueTime = std::max(nextEarliestIssueTime,
- curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
+ curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
}
const std::vector<MachineOpCode>&
- conflictVec = schedInfo.getConflictList(node->getOpCode());
+ conflictVec = schedInfo.getConflictList(node->getOpcode());
for (unsigned i=0; i < conflictVec.size(); i++)
{
MachineOpCode toOp = conflictVec[i];
- cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpCode(),toOp);
+ cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpcode(),toOp);
assert(toOp < (int) nextEarliestStartTime.size());
if (nextEarliestStartTime[toOp] < est)
nextEarliestStartTime[toOp] = est;
@@ -654,8 +630,8 @@
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
- if (! mii.isNop((*I)->getOpCode()) &&
- ! mii.isDummyPhiInstr((*I)->getOpCode()))
+ if (! mii.isNop(I->getOpcode()) &&
+ ! mii.isDummyPhiInstr(I->getOpcode()))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
@@ -667,12 +643,12 @@
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
- if (! mii.isDummyPhiInstr((*I)->getOpCode()))
+ if (! mii.isDummyPhiInstr(I->getOpcode()))
break;
- // Erase all except the dummy PHI instructions from MBB, and
+ // Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- MBB.erase(I, MBB.end());
+ while (I != MBB.end()) MBB.remove(I);
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
@@ -750,7 +726,7 @@
if (nextNode == NULL)
break; // no more instructions for this cycle
- if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0) {
+ if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
if (delaySlotInfo != NULL) {
if (indexForBreakingNode < S.nslots)
@@ -760,7 +736,7 @@
else
indexForDelayedInstr = S.getNumChoices();
}
- } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode())) {
+ } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpcode())) {
if (indexForBreakingNode < S.nslots)
// have a breaking instruction already so throw this one away
nextNode = NULL;
@@ -771,7 +747,7 @@
if (nextNode != NULL) {
S.addChoice(nextNode);
- if (S.schedInfo.isSingleIssue(nextNode->getOpCode())) {
+ if (S.schedInfo.isSingleIssue(nextNode->getOpcode())) {
assert(S.getNumChoices() == 1 &&
"Prioritizer returned invalid instr for this cycle!");
break;
@@ -796,7 +772,7 @@
// This is the common case, so handle it separately for efficiency.
if (S.getNumChoices() == 1) {
- MachineOpCode opCode = S.getChoice(0)->getOpCode();
+ MachineOpCode opCode = S.getChoice(0)->getOpcode();
unsigned int s;
for (s=startSlot; s < S.nslots; s++)
if (S.schedInfo.instrCanUseSlot(opCode, s))
@@ -805,7 +781,7 @@
S.addChoiceToSlot(s, S.getChoice(0));
} else {
for (unsigned i=0; i < S.getNumChoices(); i++) {
- MachineOpCode opCode = S.getChoice(i)->getOpCode();
+ MachineOpCode opCode = S.getChoice(i)->getOpcode();
for (unsigned int s=startSlot; s < S.nslots; s++)
if (S.schedInfo.instrCanUseSlot(opCode, s))
S.addChoiceToSlot(s, S.getChoice(i));
@@ -823,7 +799,7 @@
assert(delaySlotInfo != NULL && "No delay slot info for instr?");
const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
- MachineOpCode delayOpCode = delayedNode->getOpCode();
+ MachineOpCode delayOpCode = delayedNode->getOpcode();
unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
unsigned delayedNodeSlot = S.nslots;
@@ -841,7 +817,7 @@
for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
// Try to assign every other instruction to a lower numbered
// slot than delayedNodeSlot.
- MachineOpCode opCode =S.getChoice(i)->getOpCode();
+ MachineOpCode opCode =S.getChoice(i)->getOpcode();
bool noSlotFound = true;
unsigned int s;
for (s=startSlot; s < delayedNodeSlot; s++)
@@ -891,7 +867,7 @@
// Find the last possible slot for this instruction.
for (int s = S.nslots-1; s >= (int) startSlot; s--)
- if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s)) {
+ if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
breakingSlot = s;
break;
}
@@ -904,7 +880,7 @@
for (unsigned i=0;
i < S.getNumChoices() && i < indexForBreakingNode; i++)
{
- MachineOpCode opCode =S.getChoice(i)->getOpCode();
+ MachineOpCode opCode =S.getChoice(i)->getOpcode();
// If a higher priority instruction cannot be assigned to
// any earlier slots, don't schedule the breaking instruction.
@@ -938,7 +914,7 @@
// group, only assign them to slots lower than the breaking slot.
// Otherwise, just ignore the instruction.
for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
- MachineOpCode opCode = S.getChoice(i)->getOpCode();
+ MachineOpCode opCode = S.getChoice(i)->getOpcode();
for (unsigned int s=startSlot; s < nslotsToUse; s++)
if (S.schedInfo.instrCanUseSlot(opCode, s))
S.addChoiceToSlot(s, S.getChoice(i));
@@ -1050,11 +1026,11 @@
assert(! node->isDummyNode());
// don't put a branch in the delay slot of another branch
- if (S.getInstrInfo().isBranch(node->getOpCode()))
+ if (S.getInstrInfo().isBranch(node->getOpcode()))
return false;
// don't put a single-issue instruction in the delay slot of a branch
- if (S.schedInfo.isSingleIssue(node->getOpCode()))
+ if (S.schedInfo.isSingleIssue(node->getOpcode()))
return false;
// don't put a load-use dependence in the delay slot of a branch
@@ -1063,13 +1039,13 @@
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
- && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpCode())
+ && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false;
// for now, don't put an instruction that does not have operand
// interlocks in the delay slot of a branch
- if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
+ if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
return false;
// Finally, if the instruction precedes the branch, we make sure the
@@ -1126,7 +1102,7 @@
{
const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
- mii.getNumDelaySlots(brNode->getOpCode());
+ mii.getNumDelaySlots(brNode->getOpcode());
if (ndelays == 0)
return;
@@ -1141,10 +1117,10 @@
for (sg_pred_iterator P = pred_begin(brNode);
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
if (! (*P)->isDummyNode() &&
- ! mii.isNop((*P)->getOpCode()) &&
+ ! mii.isNop((*P)->getOpcode()) &&
NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
{
- if (mii.maxLatency((*P)->getOpCode()) > 1)
+ if (mii.maxLatency((*P)->getOpcode()) > 1)
mdelayNodeVec.push_back(*P);
else
sdelayNodeVec.push_back(*P);
@@ -1157,12 +1133,12 @@
//
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
unsigned lmin =
- mii.maxLatency(mdelayNodeVec[0]->getOpCode());
+ mii.maxLatency(mdelayNodeVec[0]->getOpcode());
unsigned minIndex = 0;
for (unsigned i=1; i < mdelayNodeVec.size(); i++)
{
unsigned li =
- mii.maxLatency(mdelayNodeVec[i]->getOpCode());
+ mii.maxLatency(mdelayNodeVec[i]->getOpcode());
if (lmin >= li)
{
lmin = li;
@@ -1190,7 +1166,7 @@
std::vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
const TargetInstrInfo& mii = S.getInstrInfo();
const MachineInstr* brInstr = node->getMachineInstr();
- unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
+ unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpcode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
// Remove the NOPs currently in delay slots from the graph.
@@ -1199,25 +1175,29 @@
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
- assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
+ MachineBasicBlock::iterator MBBI = MBB.begin();
+ std::advance(MBBI, firstDelaySlotIdx - 1);
+ assert(&*MBBI++ == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
- for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(MBB[i]->getOpCode()))
+ MachineBasicBlock::iterator Tmp = MBBI;
+ for (unsigned i = 0; i != ndelays; ++i, ++MBBI)
+ if (!mii.isNop(MBBI->getOpcode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(MBB[i]));
-
+ graph->getGraphNodeForInstr(MBBI));
+ MBBI = Tmp;
+
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
- for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(MBB[i]->getOpCode()))
+ for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx+ndelays; ++i, ++MBBI)
+ if (mii.isNop(MBBI->getOpcode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
else {
- nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
@@ -1226,7 +1206,7 @@
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if (*mciI==MBB[i])
+ if (*mciI == MBBI)
llvmMvec.erase(mciI);
}
}
@@ -1280,7 +1260,7 @@
//
unsigned first = 0;
while (first < termMvec.size() &&
- ! mii.isBranch(termMvec[first]->getOpCode()))
+ ! mii.isBranch(termMvec[first]->getOpcode()))
{
++first;
}
@@ -1305,11 +1285,9 @@
// brInstr will be NULL so this will handle the branch instrs. as well.
//
delayNodeVec.clear();
- for (unsigned i=0; i < MBB.size(); ++i)
- if (MBB[i] != brInstr &&
- mii.getNumDelaySlots(MBB[i]->getOpCode()) > 0)
- {
- SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
+ if (I != brInstr && mii.getNumDelaySlots(I->getOpcode()) > 0) {
+ SchedGraphNode* node = graph->getGraphNodeForInstr(I);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
@@ -1345,10 +1323,10 @@
for (unsigned i=0; i < delayNodeVec.size(); i++) {
const SchedGraphNode* dnode = delayNodeVec[i];
if ( ! S.isScheduled(dnode)
- && S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
- && instrIsFeasible(S, dnode->getOpCode()))
+ && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
+ && instrIsFeasible(S, dnode->getOpcode()))
{
- assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
+ assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
&& "Instructions without interlocks not yet supported "
"when filling branch delay slots");
S.scheduleInstr(dnode, nextSlot, nextTime);
Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.54 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.54.2.1
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.54 Sun Dec 14 07:24:16 2003
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Mon Mar 1 17:58:13 2004
@@ -53,9 +53,13 @@
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
- if (MI) {
- MachineOpCode mopCode = MI->getOpCode();
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
+ if (mbb) {
+ MachineBasicBlock::iterator I = MBB->begin();
+ std::advance(I, indexInBB);
+ MI = I;
+
+ MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode)
? Target.getInstrInfo().minLatency(mopCode)
: Target.getInstrInfo().maxLatency(mopCode);
@@ -100,26 +104,24 @@
}
void SchedGraph::dump() const {
- std::cerr << " Sched Graph for Basic Block: ";
- std::cerr << MBB.getBasicBlock()->getName()
- << " (" << MBB.getBasicBlock() << ")";
-
- std::cerr << "\n\n Actual Root nodes : ";
- for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
- std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
- << ((i == N-1)? "" : ", ");
-
+ std::cerr << " Sched Graph for Basic Block: "
+ << MBB.getBasicBlock()->getName()
+ << " (" << MBB.getBasicBlock() << ")"
+ << "\n\n Actual Root nodes: ";
+ for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(),
+ E = graphRoot->endOutEdges();
+ I != E; ++I) {
+ std::cerr << (*I)->getSink ()->getNodeId ();
+ if (I + 1 != E) { std::cerr << ", "; }
+ }
std::cerr << "\n Graph Nodes:\n";
- for (const_iterator I=begin(); I != end(); ++I)
+ for (const_iterator I = begin(), E = end(); I != E; ++I)
std::cerr << "\n" << *I->second;
-
std::cerr << "\n";
}
-
-
void SchedGraph::addDummyEdges() {
- assert(graphRoot->outEdges.size() == 0);
+ assert(graphRoot->getNumOutEdges() == 0);
for (const_iterator I=begin(); I != end(); ++I) {
SchedGraphNode* node = (*I).second;
@@ -142,8 +144,8 @@
// Find the first branch instr in the sequence of machine instrs for term
//
unsigned first = 0;
- while (! mii.isBranch(termMvec[first]->getOpCode()) &&
- ! mii.isReturn(termMvec[first]->getOpCode()))
+ while (! mii.isBranch(termMvec[first]->getOpcode()) &&
+ ! mii.isReturn(termMvec[first]->getOpcode()))
++first;
assert(first < termMvec.size() &&
"No branch instructions for terminator? Ok, but weird!");
@@ -161,8 +163,8 @@
assert(toNode && "No node for instr generated for branch/ret?");
for (unsigned j = i-1; j != 0; --j)
- if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
- mii.isReturn(termMvec[j-1]->getOpCode())) {
+ if (mii.isBranch(termMvec[j-1]->getOpcode()) ||
+ mii.isReturn(termMvec[j-1]->getOpcode())) {
SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
@@ -184,11 +186,11 @@
// Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again.
//
- for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (MBB[i] == termMvec[first]) // reached the first branch
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
+ if (&*I == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
@@ -200,11 +202,11 @@
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
- assert(i+d < N && "Insufficient delay slots for instruction?");
-
- for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ unsigned d = mii.getNumDelaySlots(I->getOpcode());
+
+ MachineBasicBlock::iterator J = I; ++J;
+ for (unsigned j=1; j <= d; j++, ++J) {
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
@@ -244,12 +246,12 @@
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
//
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
- MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
+ MachineOpCode fromOpCode = memNodeVec[im]->getOpcode();
int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
: (mii.isLoad(fromOpCode)? SG_LOAD_REF
: SG_STORE_REF));
for (unsigned jm=im+1; jm < NM; jm++) {
- MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
+ MachineOpCode toOpCode = memNodeVec[jm]->getOpcode();
int toType = (mii.isCall(toOpCode)? SG_CALL_REF
: (mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF));
@@ -276,7 +278,7 @@
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
//
for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
- if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
+ if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
// Add SG_CALL_REF edges from all preds to this instruction.
for (unsigned jc=0; jc < ic; jc++)
(void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
@@ -294,7 +296,7 @@
// Find the call instruction nodes and put them in a vector.
std::vector<SchedGraphNode*> callNodeVec;
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
- if (mii.isCall(memNodeVec[im]->getOpCode()))
+ if (mii.isCall(memNodeVec[im]->getOpcode()))
callNodeVec.push_back(memNodeVec[im]);
// Now walk the entire basic block, looking for CC instructions *and*
@@ -304,14 +306,14 @@
//
int lastCallNodeIdx = -1;
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
- if (mii.isCall(bbMvec[i]->getOpCode())) {
+ if (mii.isCall(bbMvec[i]->getOpcode())) {
++lastCallNodeIdx;
for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
break;
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
}
- else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
+ else if (mii.isCCInstr(bbMvec[i]->getOpcode())) {
// Add incoming/outgoing edges from/to preceding/later calls
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
int j=0;
@@ -471,7 +473,7 @@
ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = target.getInstrInfo();
- MachineOpCode opCode = node->getOpCode();
+ MachineOpCode opCode = node->getOpcode();
if (mii.isCall(opCode) || mii.isCCInstr(opCode))
callDepNodeVec.push_back(node);
@@ -488,11 +490,11 @@
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.hasAllocatedReg()) {
- int regNum = mop.getAllocatedRegNum();
+ unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
if (regNum != target.getRegInfo().getZeroRegNum())
- regToRefVecMap[mop.getAllocatedRegNum()]
+ regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
// If this is a volatile register, add the instruction to callDepVec
@@ -529,9 +531,9 @@
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
- int regNum = mop.getAllocatedRegNum();
+ unsigned regNum = mop.getReg();
if (regNum != target.getRegInfo().getZeroRegNum())
- regToRefVecMap[mop.getAllocatedRegNum()]
+ regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
}
@@ -555,10 +557,12 @@
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
- for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+ unsigned i = 0;
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
+ ++I, ++i)
+ if (!mii.isDummyPhiInstr(I->getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(MBB[i], node);
+ noteGraphNodeForInstr(I, node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -633,21 +637,12 @@
this->addCallDepEdges(callDepNodeVec, target);
// Then add incoming def-use (SSA) edges for each machine instruction.
- for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
-
-#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
- // Then add non-SSA edges for all VM instructions in the block.
- // We assume that all machine instructions that define a value are
- // generated from the VM instruction corresponding to that value.
- // TODO: This could probably be done much more efficiently.
- for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
- this->addNonSSAEdgesForValue(*II, target);
-#endif //NEED_SEPARATE_NONSSA_EDGES_CODE
-
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
+ addEdgesForInstruction(*I, valueToDefVecMap, target);
+
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
-
+
// Finally, add edges from the dummy root and to dummy leaf
this->addDummyEdges();
}
Index: llvm/lib/CodeGen/InstrSched/SchedGraph.h
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.38 llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.38.2.1
--- llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.38 Tue Jan 20 11:49:30 2004
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.h Mon Mar 1 17:58:13 2004
@@ -48,7 +48,7 @@
// Accessor methods
const MachineInstr* getMachineInstr() const { return MI; }
- const MachineOpCode getOpCode() const { return MI->getOpCode(); }
+ const MachineOpCode getOpcode() const { return MI->getOpcode(); }
bool isDummyNode() const { return (MI == NULL); }
MachineBasicBlock &getMachineBasicBlock() const { return *MBB; }
Index: llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.29 llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.29.4.1
--- llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.29 Tue Nov 11 16:41:33 2003
+++ llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp Mon Mar 1 17:58:13 2004
@@ -18,7 +18,7 @@
//===----------------------------------------------------------------------===//
#include "SchedPriorities.h"
-#include "llvm/CodeGen/FunctionLiveVarInfo.h"
+#include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h"
#include "Support/PostOrderIterator.h"
@@ -211,7 +211,7 @@
// it becomes empty.
nextChoice = candsAsHeap.getNode(mcands[nextIdx]);
if (getEarliestReadyTimeForNode(nextChoice) > curTime
- || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpCode()))
+ || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpcode()))
{
mcands.erase(mcands.begin() + nextIdx);
nextIdx = -1;
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