[llvm-commits] [parallel] CVS: llvm/include/llvm/CodeGen/LiveVariables.h MachineBasicBlock.h MachineCodeForInstruction.h MachineFrameInfo.h MachineFunction.h MachineInstr.h MachineInstrBuilder.h Passes.h SSARegMap.h SchedGraphCommon.h FunctionLiveVarInfo.h LiveIntervals.h MachineInstrAnnot.h
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 17:59:39 PST 2004
Changes in directory llvm/include/llvm/CodeGen:
LiveVariables.h updated: 1.11 -> 1.11.2.1
MachineBasicBlock.h updated: 1.13 -> 1.13.4.1
MachineCodeForInstruction.h updated: 1.12 -> 1.12.4.1
MachineFrameInfo.h updated: 1.9 -> 1.9.4.1
MachineFunction.h updated: 1.31 -> 1.31.2.1
MachineInstr.h updated: 1.118 -> 1.118.2.1
MachineInstrBuilder.h updated: 1.16 -> 1.16.4.1
Passes.h updated: 1.12 -> 1.12.2.1
SSARegMap.h updated: 1.8 -> 1.8.4.1
SchedGraphCommon.h updated: 1.9 -> 1.9.2.1
FunctionLiveVarInfo.h (r1.32) removed
LiveIntervals.h (r1.11) removed
MachineInstrAnnot.h (r1.13) removed
---
Log message:
Merge from trunk
---
Diffs of the changes: (+287 -224)
Index: llvm/include/llvm/CodeGen/LiveVariables.h
diff -u llvm/include/llvm/CodeGen/LiveVariables.h:1.11 llvm/include/llvm/CodeGen/LiveVariables.h:1.11.2.1
--- llvm/include/llvm/CodeGen/LiveVariables.h:1.11 Sun Jan 11 03:18:45 2004
+++ llvm/include/llvm/CodeGen/LiveVariables.h Mon Mar 1 17:57:19 2004
@@ -103,6 +103,12 @@
/// BBMap - Maps LLVM basic blocks to their corresponding machine basic block.
/// This also provides a numbering of the basic blocks in the function.
std::map<const BasicBlock*, std::pair<MachineBasicBlock*, unsigned> > BBMap;
+
+
+ /// BBIdxMap - This contains the inverse mapping of BBMap, going from block ID
+ /// numbers to the corresponding MachineBasicBlock. This is lazily computed
+ /// when the getIndexMachineBasicBlock() method is called.
+ std::vector<MachineBasicBlock*> BBIdxMap;
const MRegisterInfo *RegInfo;
@@ -126,6 +132,9 @@
return BBMap.find(BB)->second;
}
+ /// getIndexMachineBasicBlock() - Given a block index, return the
+ /// MachineBasicBlock corresponding to it.
+ MachineBasicBlock *getIndexMachineBasicBlock(unsigned Idx);
/// killed_iterator - Iterate over registers killed by a machine instruction
///
@@ -158,6 +167,12 @@
//===--------------------------------------------------------------------===//
// API to update live variable information
+ /// instructionChanged - When the address of an instruction changes, this
+ /// method should be called so that live variables can update its internal
+ /// data structures. This removes the records for OldMI, transfering them to
+ /// the records for NewMI.
+ void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
+
/// addVirtualRegisterKilled - Add information about the fact that the
/// specified register is killed after being used by the specified
/// instruction.
@@ -243,6 +258,7 @@
RegistersKilled.clear();
RegistersDead.clear();
BBMap.clear();
+ BBIdxMap.clear();
}
/// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h
diff -u llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.13 llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.13.4.1
--- llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.13 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/CodeGen/MachineBasicBlock.h Mon Mar 1 17:57:19 2004
@@ -14,40 +14,77 @@
#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
-#include <vector>
+#include "llvm/CodeGen/MachineInstr.h"
+#include "Support/ilist"
+#include <iosfwd>
namespace llvm {
+ class MachineFunction;
+
+// ilist_traits
+template <>
+class ilist_traits<MachineInstr> {
+ // this is only set by the MachineBasicBlock owning the ilist
+ friend class MachineBasicBlock;
+ MachineBasicBlock* parent;
+
+public:
+ ilist_traits<MachineInstr>() : parent(0) { }
+
+ static MachineInstr* getPrev(MachineInstr* N) { return N->prev; }
+ static MachineInstr* getNext(MachineInstr* N) { return N->next; }
+
+ static const MachineInstr*
+ getPrev(const MachineInstr* N) { return N->prev; }
+
+ static const MachineInstr*
+ getNext(const MachineInstr* N) { return N->next; }
+
+ static void setPrev(MachineInstr* N, MachineInstr* prev) { N->prev = prev; }
+ static void setNext(MachineInstr* N, MachineInstr* next) { N->next = next; }
+
+ static MachineInstr* createNode();
+ void addNodeToList(MachineInstr* N);
+ void removeNodeFromList(MachineInstr* N);
+ void transferNodesFromList(
+ iplist<MachineInstr, ilist_traits<MachineInstr> >& toList,
+ ilist_iterator<MachineInstr> first,
+ ilist_iterator<MachineInstr> last);
+};
class BasicBlock;
-class MachineInstr;
-template <typename T> struct ilist_traits;
class MachineBasicBlock {
- std::vector<MachineInstr*> Insts;
+public:
+ typedef ilist<MachineInstr> Instructions;
+ Instructions Insts;
MachineBasicBlock *Prev, *Next;
const BasicBlock *BB;
public:
- MachineBasicBlock(const BasicBlock *bb = 0) : Prev(0), Next(0), BB(bb) {}
+ MachineBasicBlock(const BasicBlock *bb = 0) : Prev(0), Next(0), BB(bb) {
+ Insts.parent = this;
+ }
~MachineBasicBlock() {}
/// getBasicBlock - Return the LLVM basic block that this instance
/// corresponded to originally.
///
const BasicBlock *getBasicBlock() const { return BB; }
-
- typedef std::vector<MachineInstr*>::iterator iterator;
- typedef std::vector<MachineInstr*>::const_iterator const_iterator;
+
+ /// getParent - Return the MachineFunction containing this basic block.
+ ///
+ const MachineFunction *getParent() const;
+
+ typedef ilist<MachineInstr>::iterator iterator;
+ typedef ilist<MachineInstr>::const_iterator const_iterator;
typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
typedef std::reverse_iterator<iterator> reverse_iterator;
unsigned size() const { return Insts.size(); }
bool empty() const { return Insts.empty(); }
- MachineInstr * operator[](unsigned i) const { return Insts[i]; }
- MachineInstr *&operator[](unsigned i) { return Insts[i]; }
-
- MachineInstr *front() const { return Insts.front(); }
- MachineInstr *back() const { return Insts.back(); }
+ MachineInstr& front() { return Insts.front(); }
+ MachineInstr& back() { return Insts.back(); }
iterator begin() { return Insts.begin(); }
const_iterator begin() const { return Insts.begin(); }
@@ -58,22 +95,26 @@
reverse_iterator rend () { return Insts.rend(); }
const_reverse_iterator rend () const { return Insts.rend(); }
+ /// getFirstTerminator - returns an iterator to the first terminator
+ /// instruction of this basic block. If a terminator does not exist,
+ /// it returns end()
+ iterator getFirstTerminator();
+
void push_back(MachineInstr *MI) { Insts.push_back(MI); }
template<typename IT>
void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); }
iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); }
// erase - Remove the specified element or range from the instruction list.
- // These functions do not delete any instructions removed.
+ // These functions delete any instructions removed.
//
iterator erase(iterator I) { return Insts.erase(I); }
iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }
+ MachineInstr* remove(iterator &I) { return Insts.remove(I); }
- MachineInstr *pop_back() {
- MachineInstr *R = back();
- Insts.pop_back();
- return R;
- }
+ // Debugging methods.
+ void dump() const;
+ void print(std::ostream &OS) const;
private: // Methods used to maintain doubly linked list of blocks...
friend class ilist_traits<MachineBasicBlock>;
Index: llvm/include/llvm/CodeGen/MachineCodeForInstruction.h
diff -u llvm/include/llvm/CodeGen/MachineCodeForInstruction.h:1.12 llvm/include/llvm/CodeGen/MachineCodeForInstruction.h:1.12.4.1
--- llvm/include/llvm/CodeGen/MachineCodeForInstruction.h:1.12 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/CodeGen/MachineCodeForInstruction.h Mon Mar 1 17:57:19 2004
@@ -45,14 +45,8 @@
MachineCodeForInstruction() : Annotation(MCFI_AID), callArgsDesc(NULL) {}
~MachineCodeForInstruction();
- static MachineCodeForInstruction &get(const Instruction *I) {
- assert(I != NULL);
- return *(MachineCodeForInstruction*)
- ((Annotable*)I)->getOrCreateAnnotation(MCFI_AID);
- }
- static void destroy(const Instruction *I) {
- ((Annotable*)I)->deleteAnnotation(MCFI_AID);
- }
+ static MachineCodeForInstruction &get(const Instruction *I);
+ static void destroy(const Instruction *I);
// Access to underlying machine instructions...
typedef std::vector<MachineInstr*>::iterator iterator;
Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h
diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.9 llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.9.4.1
--- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.9 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/CodeGen/MachineFrameInfo.h Mon Mar 1 17:57:19 2004
@@ -38,18 +38,13 @@
#ifndef LLVM_CODEGEN_MACHINEFRAMEINFO_H
#define LLVM_CODEGEN_MACHINEFRAMEINFO_H
-namespace llvm {
+#include <vector>
+namespace llvm {
class TargetData;
class TargetRegisterClass;
class Type;
class MachineFunction;
-
-}
-
-#include <vector>
-
-namespace llvm {
class MachineFrameInfo {
Index: llvm/include/llvm/CodeGen/MachineFunction.h
diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.31 llvm/include/llvm/CodeGen/MachineFunction.h:1.31.2.1
--- llvm/include/llvm/CodeGen/MachineFunction.h:1.31 Sat Dec 20 04:18:58 2003
+++ llvm/include/llvm/CodeGen/MachineFunction.h Mon Mar 1 17:57:19 2004
@@ -20,7 +20,6 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "Support/Annotation.h"
-#include "Support/ilist"
namespace llvm {
Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.118 llvm/include/llvm/CodeGen/MachineInstr.h:1.118.2.1
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.118 Sun Dec 14 07:30:19 2003
+++ llvm/include/llvm/CodeGen/MachineInstr.h Mon Mar 1 17:57:19 2004
@@ -16,9 +16,9 @@
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/Target/MRegisterInfo.h"
-#include "Support/Annotation.h"
#include "Support/iterator"
+#include <vector>
+#include <cassert>
namespace llvm {
@@ -28,33 +28,10 @@
class TargetMachine;
class GlobalValue;
-typedef int MachineOpCode;
+template <typename T> class ilist_traits;
+template <typename T> class ilist;
-//===----------------------------------------------------------------------===//
-/// Special flags on instructions that modify the opcode.
-/// These flags are unused for now, but having them enforces that some
-/// changes will be needed if they are used.
-///
-enum MachineOpCodeFlags {
- AnnulFlag, /// 1 if annul bit is set on a branch
- PredTakenFlag, /// 1 if branch should be predicted taken
- PredNotTakenFlag /// 1 if branch should be predicted not taken
-};
-
-//===----------------------------------------------------------------------===//
-/// MOTy - MachineOperandType - This namespace contains an enum that describes
-/// how the machine operand is used by the instruction: is it read, defined, or
-/// both? Note that the MachineInstr/Operator class currently uses bool
-/// arguments to represent this information instead of an enum. Eventually this
-/// should change over to use this _easier to read_ representation instead.
-///
-namespace MOTy {
- enum UseType {
- Use, /// This machine operand is only read by the instruction
- Def, /// This machine operand is only written by the instruction
- UseAndDef /// This machine operand is read AND written
- };
-}
+typedef short MachineOpCode;
//===----------------------------------------------------------------------===//
// class MachineOperand
@@ -92,6 +69,31 @@
//===----------------------------------------------------------------------===//
struct MachineOperand {
+private:
+ // Bit fields of the flags variable used for different operand properties
+ enum {
+ DEFFLAG = 0x01, // this is a def of the operand
+ USEFLAG = 0x02, // this is a use of the operand
+ HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
+ LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
+ HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
+ LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
+ PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
+ };
+
+public:
+ // UseType - This enum describes how the machine operand is used by
+ // the instruction. Note that the MachineInstr/Operator class
+ // currently uses bool arguments to represent this information
+ // instead of an enum. Eventually this should change over to use
+ // this _easier to read_ representation instead.
+ //
+ enum UseType {
+ Use = USEFLAG, /// only read
+ Def = DEFFLAG, /// only written
+ UseAndDef = Use | Def /// read AND written
+ };
+
enum MachineOperandType {
MO_VirtualRegister, // virtual register for *value
MO_MachineRegister, // pre-assigned machine register `regNum'
@@ -107,18 +109,6 @@
};
private:
- // Bit fields of the flags variable used for different operand properties
- enum {
- DEFFLAG = 0x01, // this is a def of the operand
- USEFLAG = 0x02, // this is a use of the operand
- HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
- LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
- HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
- LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
- PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
- };
-
-private:
union {
Value* value; // BasicBlockVal for a label operand.
// ConstantVal for a non-address immediate.
@@ -127,7 +117,7 @@
// the generated machine code.
// LLVM global for MO_GlobalAddress.
- int64_t immedVal; // Constant value for an explicit constant
+ int immedVal; // Constant value for an explicit constant
MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
std::string *SymbolName; // For MO_ExternalSymbol type
@@ -138,44 +128,25 @@
int regNum; // register number for an explicit register
// will be set for a value after reg allocation
private:
- MachineOperand()
- : immedVal(0),
- flags(0),
- opType(MO_VirtualRegister),
- regNum(-1) {}
-
- MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
+ MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
: immedVal(ImmVal),
flags(0),
opType(OpTy),
regNum(-1) {}
- MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
- : immedVal(0),
- opType(OpTy),
- regNum(Reg) {
- switch (UseTy) {
- case MOTy::Use: flags = USEFLAG; break;
- case MOTy::Def: flags = DEFFLAG; break;
- case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
- default: assert(0 && "Invalid value for UseTy!");
- }
- }
+ MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
+ : immedVal(0), flags(UseTy), opType(OpTy), regNum(Reg) { }
- MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
+ MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
bool isPCRelative = false)
- : value(V), opType(OpTy), regNum(-1) {
- switch (UseTy) {
- case MOTy::Use: flags = USEFLAG; break;
- case MOTy::Def: flags = DEFFLAG; break;
- case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
- default: assert(0 && "Invalid value for UseTy!");
- }
- if (isPCRelative) flags |= PCRELATIVE;
+ : value(V),
+ flags(UseTy | (isPCRelative ? PCRELATIVE : 0)),
+ opType(OpTy),
+ regNum(-1) {
}
MachineOperand(MachineBasicBlock *mbb)
- : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
+ : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) { }
MachineOperand(const std::string &SymName, bool isPCRelative)
: SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
@@ -207,11 +178,16 @@
return *this;
}
- // Accessor methods. Caller is responsible for checking the
- // operand type before invoking the corresponding accessor.
- //
+ /// getType - Returns the MachineOperandType for this operand.
+ ///
MachineOperandType getType() const { return opType; }
+ /// getUseType - Returns the MachineOperandUseType of this operand.
+ ///
+ UseType getUseType() const {
+ return UseType(flags & (USEFLAG|DEFFLAG));
+ }
+
/// isPCRelative - This returns the value of the PCRELATIVE flag, which
/// indicates whether this operand should be emitted as a PC relative value
/// instead of a global address. This is used for operands of the forms:
@@ -219,22 +195,16 @@
///
bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
-
- // This is to finally stop caring whether we have a virtual or machine
- // register -- an easier interface is to simply call both virtual and machine
- // registers essentially the same, yet be able to distinguish when
- // necessary. Thus the instruction selector can just add registers without
- // abandon, and the register allocator won't be confused.
- bool isVirtualRegister() const {
- return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
- && regNum >= MRegisterInfo::FirstVirtualRegister;
- }
- bool isPhysicalRegister() const {
- return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
- && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
+ /// isRegister - Return true if this operand is a register operand. The X86
+ /// backend currently can't decide whether to use MO_MR or MO_VR to represent
+ /// them, so we accept both.
+ ///
+ /// Note: The sparc backend should not use this method.
+ ///
+ bool isRegister() const {
+ return opType == MO_MachineRegister || opType == MO_VirtualRegister;
}
- bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
- bool isMachineRegister() const { return !isVirtualRegister(); }
+
bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
bool isImmediate() const {
@@ -258,8 +228,8 @@
assert(opType == MO_MachineRegister);
return regNum;
}
- int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
- void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
+ int getImmedValue() const { assert(isImmediate()); return immedVal; }
+ void setImmedValue(int ImmVal) { assert(isImmediate()); immedVal = ImmVal; }
MachineBasicBlock *getMachineBasicBlock() const {
assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
@@ -281,12 +251,14 @@
return *SymbolName;
}
- bool isUse () const { return flags & USEFLAG; }
- bool isDef () const { return flags & DEFFLAG; }
- bool isHiBits32 () const { return flags & HIFLAG32; }
- bool isLoBits32 () const { return flags & LOFLAG32; }
- bool isHiBits64 () const { return flags & HIFLAG64; }
- bool isLoBits64 () const { return flags & LOFLAG64; }
+ bool isUse () const { return flags & USEFLAG; }
+ MachineOperand& setUse () { flags |= USEFLAG; return *this; }
+ bool isDef () const { return flags & DEFFLAG; }
+ MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
+ bool isHiBits32 () const { return flags & HIFLAG32; }
+ bool isLoBits32 () const { return flags & LOFLAG32; }
+ bool isHiBits64 () const { return flags & HIFLAG64; }
+ bool isLoBits64 () const { return flags & LOFLAG64; }
// used to check if a machine register has been allocated to this operand
bool hasAllocatedReg() const {
@@ -296,15 +268,12 @@
}
// used to get the reg number if when one is allocated
- int getAllocatedRegNum() const {
+ unsigned getReg() const {
assert(hasAllocatedReg());
return regNum;
}
// ********** TODO: get rid of this duplicate code! ***********
- unsigned getReg() const {
- return getAllocatedRegNum();
- }
void setReg(unsigned Reg) {
assert(hasAllocatedReg() && "This operand cannot have a register number!");
regNum = Reg;
@@ -352,45 +321,49 @@
//===----------------------------------------------------------------------===//
class MachineInstr {
- int opCode; // the opcode
- unsigned opCodeFlags; // flags modifying instrn behavior
+ short Opcode; // the opcode
+ unsigned char numImplicitRefs; // number of implicit operands
std::vector<MachineOperand> operands; // the operands
- unsigned numImplicitRefs; // number of implicit operands
-
+ MachineInstr* prev, *next; // links for our intrusive list
+ MachineBasicBlock* parent; // pointer to the owning basic block
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
+
+private:
+ // Intrusive list support
+ //
+ friend class ilist_traits<MachineInstr>;
+
public:
- MachineInstr(int Opcode, unsigned numOperands);
+ MachineInstr(short Opcode, unsigned numOperands);
/// MachineInstr ctor - This constructor only does a _reserve_ of the
/// operands, not a resize for them. It is expected that if you use this that
/// you call add* methods below to fill up the operands, instead of the Set
/// methods. Eventually, the "resizing" ctors will be phased out.
///
- MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
+ MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
- MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
+ MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
+ ~MachineInstr();
- // The opcode.
- //
- const int getOpcode() const { return opCode; }
- const int getOpCode() const { return opCode; }
+ const MachineBasicBlock* getParent() const { return parent; }
+ MachineBasicBlock* getParent() { return parent; }
- // Opcode flags.
- //
- unsigned getOpCodeFlags() const { return opCodeFlags; }
+ /// Accessors for opcode.
+ ///
+ const int getOpcode() const { return Opcode; }
- //
- // Access to explicit operands of the instruction
- //
+ /// Access to explicit operands of the instruction.
+ ///
unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
const MachineOperand& getOperand(unsigned i) const {
@@ -472,19 +445,24 @@
void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
- !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
+ operands.push_back(
+ MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ !isDef ? MachineOperand::Use :
+ (isDefAndUse ? MachineOperand::UseAndDef :
+ MachineOperand::Def)));
}
- void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
- bool isPCRelative = false) {
+ void addRegOperand(Value *V,
+ MachineOperand::UseType UTy = MachineOperand::Use,
+ bool isPCRelative = false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
UTy, isPCRelative));
}
- void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
+ void addCCRegOperand(Value *V,
+ MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
@@ -497,17 +475,19 @@
void addRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
- isDef ? MOTy::Def : MOTy::Use));
+ operands.push_back(
+ MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addRegOperand - Add a symbolic virtual register reference...
///
- void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ void addRegOperand(int reg,
+ MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
- UTy));
+ operands.push_back(
+ MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
}
/// addPCDispOperand - Add a PC relative displacement operand to the MI
@@ -515,8 +495,8 @@
void addPCDispOperand(Value *V) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
- MOTy::Use));
+ operands.push_back(
+ MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
@@ -524,37 +504,39 @@
void addMachineRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
- isDef ? MOTy::Def : MOTy::Use));
+ operands.push_back(
+ MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
///
- void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ void addMachineRegOperand(int reg,
+ MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
- UTy));
+ operands.push_back(
+ MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
}
/// addZeroExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
- void addZeroExtImmOperand(int64_t intValue) {
+ void addZeroExtImmOperand(int intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(intValue,
- MachineOperand::MO_UnextendedImmed));
+ operands.push_back(
+ MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
}
/// addSignExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
- void addSignExtImmOperand(int64_t intValue) {
+ void addSignExtImmOperand(int intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(intValue,
- MachineOperand::MO_SignExtendedImmed));
+ operands.push_back(
+ MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed));
}
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
@@ -583,9 +565,9 @@
void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand((Value*)GV,
- MachineOperand::MO_GlobalAddress,
- MOTy::Use, isPCRelative));
+ operands.push_back(
+ MachineOperand((Value*)GV, MachineOperand::MO_GlobalAddress,
+ MachineOperand::Use, isPCRelative));
}
/// addExternalSymbolOperand - Add an external symbol operand to this instr
@@ -603,11 +585,11 @@
/// simply replace() and then set new operands with Set.*Operand methods
/// below.
///
- void replace(int Opcode, unsigned numOperands);
+ void replace(short Opcode, unsigned numOperands);
/// setOpcode - Replace the opcode of the current instruction with a new one.
///
- void setOpcode(unsigned Op) { opCode = Op; }
+ void setOpcode(unsigned Op) { Opcode = Op; }
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
@@ -618,13 +600,13 @@
// Access to set the operands when building the machine instruction
//
- void SetMachineOperandVal (unsigned i,
- MachineOperand::MachineOperandType operandType,
- Value* V);
-
- void SetMachineOperandConst (unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue);
+ void SetMachineOperandVal(unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ Value* V);
+
+ void SetMachineOperandConst(unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ int intValue);
void SetMachineOperandReg(unsigned i, int regNum);
@@ -710,7 +692,6 @@
return const_val_op_iterator::end(this);
}
};
-
//===----------------------------------------------------------------------===//
// Debugging Support
Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h
diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.16 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.16.4.1
--- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.16 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Mon Mar 1 17:57:19 2004
@@ -23,7 +23,7 @@
#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
namespace llvm {
@@ -38,33 +38,36 @@
/// addReg - Add a new virtual register operand...
///
- const MachineInstrBuilder &addReg(int RegNo,
- MOTy::UseType Ty = MOTy::Use) const {
+ const MachineInstrBuilder &addReg(
+ int RegNo,
+ MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(RegNo, Ty);
return *this;
}
/// addReg - Add an LLVM value that is to be used as a register...
///
- const MachineInstrBuilder &addReg(Value *V,
- MOTy::UseType Ty = MOTy::Use) const {
+ const MachineInstrBuilder &addReg(
+ Value *V,
+ MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(V, Ty);
return *this;
}
/// addReg - Add an LLVM value that is to be used as a register...
///
- const MachineInstrBuilder &addCCReg(Value *V,
- MOTy::UseType Ty = MOTy::Use) const {
+ const MachineInstrBuilder &addCCReg(
+ Value *V,
+ MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addCCRegOperand(V, Ty);
return *this;
}
/// addRegDef - Add an LLVM value that is to be defined as a register... this
- /// is the same as addReg(V, MOTy::Def).
+ /// is the same as addReg(V, MachineOperand::Def).
///
const MachineInstrBuilder &addRegDef(Value *V) const {
- return addReg(V, MOTy::Def);
+ return addReg(V, MachineOperand::Def);
}
/// addPCDisp - Add an LLVM value to be treated as a PC relative
@@ -77,22 +80,29 @@
/// addMReg - Add a machine register operand...
///
- const MachineInstrBuilder &addMReg(int Reg,
- MOTy::UseType Ty = MOTy::Use) const {
+ const MachineInstrBuilder &addMReg(int Reg, MachineOperand::UseType Ty
+ = MachineOperand::Use) const {
MI->addMachineRegOperand(Reg, Ty);
return *this;
}
+
+ /// addImm - Add a new immediate operand.
+ ///
+ const MachineInstrBuilder &addImm(int Val) const {
+ MI->addZeroExtImmOperand(Val);
+ return *this;
+ }
/// addSImm - Add a new sign extended immediate operand...
///
- const MachineInstrBuilder &addSImm(int64_t val) const {
+ const MachineInstrBuilder &addSImm(int val) const {
MI->addSignExtImmOperand(val);
return *this;
}
/// addZImm - Add a new zero extended immediate operand...
///
- const MachineInstrBuilder &addZImm(int64_t Val) const {
+ const MachineInstrBuilder &addZImm(unsigned Val) const {
MI->addZeroExtImmOperand(Val);
return *this;
}
@@ -137,19 +147,42 @@
/// destination virtual register. NumOperands is the number of additional add*
/// calls that are expected, it does not include the destination register.
///
-inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands,
- unsigned DestReg) {
+inline MachineInstrBuilder BuildMI(
+ int Opcode, unsigned NumOperands,
+ unsigned DestReg,
+ MachineOperand::UseType useType = MachineOperand::Def) {
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1,
- true, true)).addReg(DestReg, MOTy::Def);
+ true, true)).addReg(DestReg, useType);
}
+/// BuildMI - Insert the instruction before a specified location in the basic
+/// block.
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ int Opcode, unsigned NumOperands,
+ unsigned DestReg) {
+ MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
+ BB.insert(I, MI);
+ return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
+}
+
+/// BMI - A special BuildMI variant that takes an iterator to insert the
+/// instruction at as well as a basic block.
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ int Opcode, unsigned NumOperands) {
+ MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
+ BB.insert(I, MI);
+ return MachineInstrBuilder(MI);
+}
+
/// BuildMI - This version of the builder inserts the built MachineInstr into
/// the specified MachineBasicBlock.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
unsigned NumOperands) {
- return MachineInstrBuilder(new MachineInstr(BB, Opcode, NumOperands));
+ return BuildMI(*BB, BB->end(), Opcode, NumOperands);
}
/// BuildMI - This version of the builder inserts the built MachineInstr into
@@ -159,9 +192,7 @@
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
unsigned NumOperands, unsigned DestReg) {
- return MachineInstrBuilder(new MachineInstr(BB, Opcode,
- NumOperands+1)).addReg(DestReg,
- MOTy::Def);
+ return BuildMI(*BB, BB->end(), Opcode, NumOperands, DestReg);
}
} // End llvm namespace
Index: llvm/include/llvm/CodeGen/Passes.h
diff -u llvm/include/llvm/CodeGen/Passes.h:1.12 llvm/include/llvm/CodeGen/Passes.h:1.12.2.1
--- llvm/include/llvm/CodeGen/Passes.h:1.12 Sat Dec 20 04:18:58 2003
+++ llvm/include/llvm/CodeGen/Passes.h Mon Mar 1 17:57:19 2004
@@ -15,6 +15,9 @@
#ifndef LLVM_CODEGEN_PASSES_H
#define LLVM_CODEGEN_PASSES_H
+#include <iosfwd>
+#include <string>
+
namespace llvm {
class FunctionPass;
@@ -23,8 +26,9 @@
/// MachineFunctionPrinter pass - This pass prints out the machine function to
/// standard error, as a debugging tool.
- FunctionPass *createMachineFunctionPrinterPass();
-
+ FunctionPass *createMachineFunctionPrinterPass(std::ostream *OS,
+ const std::string &Banner ="");
+
/// PHIElimination pass - This pass eliminates machine instruction PHI nodes
/// by inserting copy instructions. This destroys SSA information, but is the
/// desired input for some register allocators. This pass is "required" by
Index: llvm/include/llvm/CodeGen/SSARegMap.h
diff -u llvm/include/llvm/CodeGen/SSARegMap.h:1.8 llvm/include/llvm/CodeGen/SSARegMap.h:1.8.4.1
--- llvm/include/llvm/CodeGen/SSARegMap.h:1.8 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/CodeGen/SSARegMap.h Mon Mar 1 17:57:19 2004
@@ -1,48 +1,51 @@
//===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Map register numbers to register classes that are correctly sized (typed) to
// hold the information. Assists register allocation. Contained by
// MachineFunction, should be deleted by register allocator when it is no
// longer needed.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SSAREGMAP_H
#define LLVM_CODEGEN_SSAREGMAP_H
#include "llvm/Target/MRegisterInfo.h"
+#include "Support/DenseMap.h"
namespace llvm {
class TargetRegisterClass;
class SSARegMap {
- std::vector<const TargetRegisterClass*> RegClassMap;
-
- unsigned rescale(unsigned Reg) {
- return Reg - MRegisterInfo::FirstVirtualRegister;
- }
+ DenseMap<const TargetRegisterClass*, VirtReg2IndexFunctor> RegClassMap;
+ unsigned NextRegNum;
public:
+ SSARegMap() : NextRegNum(MRegisterInfo::FirstVirtualRegister) { }
+
const TargetRegisterClass* getRegClass(unsigned Reg) {
- unsigned actualReg = rescale(Reg);
- assert(actualReg < RegClassMap.size() && "Register out of bounds");
- return RegClassMap[actualReg];
+ return RegClassMap[Reg];
}
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
///
unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
- RegClassMap.push_back(RegClass);
- return RegClassMap.size()+MRegisterInfo::FirstVirtualRegister-1;
+ RegClassMap.grow(NextRegNum);
+ RegClassMap[NextRegNum] = RegClass;
+ return NextRegNum++;
+ }
+
+ unsigned getLastVirtReg() const {
+ return NextRegNum - 1;
}
};
Index: llvm/include/llvm/CodeGen/SchedGraphCommon.h
diff -u llvm/include/llvm/CodeGen/SchedGraphCommon.h:1.9 llvm/include/llvm/CodeGen/SchedGraphCommon.h:1.9.2.1
--- llvm/include/llvm/CodeGen/SchedGraphCommon.h:1.9 Tue Jan 20 11:49:42 2004
+++ llvm/include/llvm/CodeGen/SchedGraphCommon.h Mon Mar 1 17:57:19 2004
@@ -72,7 +72,6 @@
virtual void print(std::ostream &os) const = 0;
protected:
- friend class SchedGraph;
friend class SchedGraphCommon;
friend class SchedGraphEdge; // give access for adding edges
More information about the llvm-commits
mailing list