[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sat Feb 28 23:59:01 PST 2004
Changes in directory llvm/lib/Target/SparcV9:
SparcV9InstrSelection.cpp updated: 1.134 -> 1.135
---
Log message:
This is the only file in the system that uses this enum. eliminate it.
---
Diffs of the changes: (+6 -6)
Index: llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.134 llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.135
--- llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.134 Wed Feb 25 12:44:15 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp Sat Feb 28 23:57:59 2004
@@ -915,7 +915,7 @@
Value* lval, Value* rval, Instruction* destVal,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi,
- MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
+ MachineOpCode forceMulOp = -1)
{
unsigned L = mvec.size();
CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
@@ -923,7 +923,7 @@
// no instructions were added so create MUL reg, reg, reg.
// Use FSMULD if both operands are actually floats cast to doubles.
// Otherwise, use the default opcode for the appropriate type.
- MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
+ MachineOpCode mulOp = ((forceMulOp != -1)
? forceMulOp
: ChooseMulInstructionByType(destVal->getType()));
mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
@@ -1115,7 +1115,7 @@
// Instruction 1: mul numElements, typeSize -> tmpProd
// This will optimize the MUL as far as possible.
CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd, getMvec,
- mcfi, INVALID_MACHINE_OPCODE);
+ mcfi, -1);
// Instruction 2: andn tmpProd, 0x0f -> tmpAndn
getMvec.push_back(BuildMI(V9::ADDi, 3).addReg(tmpProd).addSImm(15)
@@ -1278,7 +1278,7 @@
eltSizeVal, /* rval, likely to be constant */
addr, /* result */
mulVec, MachineCodeForInstruction::get(memInst),
- INVALID_MACHINE_OPCODE);
+ -1);
assert(mulVec.size() > 0 && "No multiply code created?");
mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
@@ -2007,7 +2007,7 @@
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
? (MachineOpCode)V9::FSMULD
- : INVALID_MACHINE_OPCODE);
+ : -1);
Instruction* mulInstr = subtreeRoot->getInstruction();
CreateMulInstruction(target, mulInstr->getParent()->getParent(),
subtreeRoot->leftChild()->getValue(),
@@ -2025,7 +2025,7 @@
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
? (MachineOpCode)V9::FSMULD
- : INVALID_MACHINE_OPCODE);
+ : -1);
Instruction* mulInstr = subtreeRoot->getInstruction();
CreateMulInstruction(target, mulInstr->getParent()->getParent(),
subtreeRoot->leftChild()->getValue(),
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