[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td SparcV8InstrInfo_F2.td SparcV8InstrInfo_F3.td SparcV8RegisterInfo.td SparcV8.td SparcV8Instrs.td SparcV8Instrs_F2.td SparcV8Instrs_F3.td SparcV8Reg.td
Chris Lattner
lattner at cs.uiuc.edu
Sat Feb 28 13:46:01 PST 2004
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td added (r1.1)
SparcV8InstrInfo_F2.td added (r1.1)
SparcV8InstrInfo_F3.td added (r1.1)
SparcV8RegisterInfo.td added (r1.1)
SparcV8.td updated: 1.2 -> 1.3
SparcV8Instrs.td (r1.5) removed
SparcV8Instrs_F2.td (r1.2) removed
SparcV8Instrs_F3.td (r1.2) removed
SparcV8Reg.td (r1.3) removed
---
Log message:
Tab completion is our friend.
---
Diffs of the changes: (+218 -2)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.1
*** /dev/null Sat Feb 28 13:45:49 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Sat Feb 28 13:45:39 2004
***************
*** 0 ****
--- 1,68 ----
+ //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file describes the SparcV8 instructions in TableGen format.
+ //
+ //===----------------------------------------------------------------------===//
+
+ //===----------------------------------------------------------------------===//
+ // Instruction format superclass
+ //===----------------------------------------------------------------------===//
+
+ class InstV8 : Instruction { // SparcV8 instruction baseline
+ field bits<32> Inst;
+
+ let Namespace = "V8";
+
+ bits<2> op;
+ let Inst{31-30} = op; // Top two bits are the 'op' field
+
+ // Bit attributes specific to SparcV8 instructions
+ bit isPasi = 0; // Does this instruction affect an alternate addr space?
+ bit isPrivileged = 0; // Is this a privileged instruction?
+ }
+
+ include "SparcV8InstrInfo_F2.td"
+ include "SparcV8InstrInfo_F3.td"
+
+ //===----------------------------------------------------------------------===//
+ // Instructions
+ //===----------------------------------------------------------------------===//
+
+ // Pseudo instructions.
+ def PHI : InstV8 {
+ let Name = "PHI";
+ }
+ def ADJCALLSTACKDOWN : InstV8 {
+ let Name = "ADJCALLSTACKDOWN";
+ }
+ def ADJCALLSTACKUP : InstV8 {
+ let Name = "ADJCALLSTACKUP";
+ }
+
+ // Section B.20: SAVE and RESTORE - p117
+ def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
+ def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
+ def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
+ def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
+
+ // Section B.24: Call and Link - p125
+ // This is the only Format 1 instruction
+ def CALL : InstV8 {
+ bits<30> disp;
+
+ let op = 1;
+ let Inst{29-0} = disp;
+ let Name = "call";
+ }
+
+ // Section B.25: Jump and Link - p126
+ def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
+ def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
+
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td:1.1
*** /dev/null Sat Feb 28 13:45:49 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td Sat Feb 28 13:45:39 2004
***************
*** 0 ****
--- 1,44 ----
+ //===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Format #2 instruction classes in the SparcV8
+ //
+ //===----------------------------------------------------------------------===//
+
+ class F2 : InstV8 { // Format 2 instructions
+ bits<3> op2;
+ bits<22> imm22;
+ let op = 0; // op = 0
+ let Inst{24-22} = op2;
+ let Inst{21-0} = imm22;
+ }
+
+ // Specific F2 classes: SparcV8 manual, page 44
+ //
+ class F2_1<bits<3> op2Val, string name> : F2 {
+ bits<5> rd;
+ bits<22> imm;
+
+ let op2 = op2Val;
+ let Name = name;
+
+ let Inst{29-25} = rd;
+ }
+
+ class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
+ bits<4> cond;
+ bit annul = 0; // currently unused
+
+ let cond = condVal;
+ let op2 = op2Val;
+ let Name = name;
+
+ let Inst{29} = annul;
+ let Inst{28-25} = cond;
+ }
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td:1.1
*** /dev/null Sat Feb 28 13:45:49 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td Sat Feb 28 13:45:39 2004
***************
*** 0 ****
--- 1,62 ----
+ //===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Format #3 instruction classes in the SparcV8
+ //
+ //===----------------------------------------------------------------------===//
+
+ class F3 : InstV8 {
+ bits<5> rd;
+ bits<6> op3;
+ bits<5> rs1;
+ let op{1} = 1; // Op = 2 or 3
+ let Inst{29-25} = rd;
+ let Inst{24-19} = op3;
+ let Inst{18-14} = rs1;
+ }
+
+ // Specific F3 classes: SparcV8 manual, page 44
+ //
+ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
+ bits<8> asi;
+ bits<5> rs2;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13} = 0; // i field = 0
+ let Inst{12-5} = asi; // address space identifier
+ let Inst{4-0} = rs2;
+ }
+
+ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
+ bits<13> simm13;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13} = 1; // i field = 1
+ let Inst{12-0} = simm13;
+ }
+
+ /*
+ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
+ : F3_rs1rs2 {
+ bits<5> rs2;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13-5} = opfVal;
+ let Inst{4-0} = rs2;
+ }
+ */
\ No newline at end of file
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.1
*** /dev/null Sat Feb 28 13:45:49 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td Sat Feb 28 13:45:39 2004
***************
*** 0 ****
--- 1,42 ----
+ //===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Declarations that describe the SparcV8 register file
+ //
+ //===----------------------------------------------------------------------===//
+
+ // Ri - 32-bit integer registers
+ class Ri<bits<5> num> : Register {
+ field bits<5> Num = num; // Numbers are identified with a 5 bit ID
+ }
+
+ let Namespace = "SparcV8" in {
+ def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
+ def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
+ def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
+ def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
+ def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
+ def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
+ def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
+ def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
+
+ // Floating-point registers?
+ // ...
+ }
+
+
+ // For fun, specify a register class.
+ //
+ // FIXME: the register order should be defined in terms of the preferred
+ // allocation order...
+ //
+ def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O6, O7,
+ L0, L1, L2, L3, L4, L5, L6, L7,
+ I0, I1, I2, I3, I4, I5, I6, I7]>;
Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -u llvm/lib/Target/SparcV8/SparcV8.td:1.2 llvm/lib/Target/SparcV8/SparcV8.td:1.3
--- llvm/lib/Target/SparcV8/SparcV8.td:1.2 Wed Feb 25 15:02:21 2004
+++ llvm/lib/Target/SparcV8/SparcV8.td Sat Feb 28 13:45:39 2004
@@ -18,8 +18,8 @@
// Register File Description
//===----------------------------------------------------------------------===//
-include "SparcV8Reg.td"
-include "SparcV8Instrs.td"
+include "SparcV8RegisterInfo.td"
+include "SparcV8InstrInfo.td"
def SparcV8InstrInfo : InstrInfo {
let PHIInst = PHI;
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