[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Chris Lattner
sabre at nondot.org
Fri Feb 27 22:34:00 PST 2004
On Fri, 27 Feb 2004, Chris Lattner wrote:
> I vaguely recall that this issue came up with some other instruction, but
> can't remember which one off-hand. I think it was a sign extension or
> something like that that dealt with mixed size operands.
Hrm, I think it was one of the "short forms". Operations like:
[mem32] += imm8
need this.
-Chris
> > Index: llvm/lib/Target/X86/X86InstrInfo.td
> > diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.47 llvm/lib/Target/X86/X86InstrInfo.td:1.48
> > --- llvm/lib/Target/X86/X86InstrInfo.td:1.47 Fri Feb 27 13:46:30 2004
> > +++ llvm/lib/Target/X86/X86InstrInfo.td Fri Feb 27 20:56:26 2004
> > @@ -462,11 +462,11 @@
> > def SHLmCL32 : I2A32<"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
> >
> > def SHLri8 : I2A8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
> > -def SHLri16 : I2A16<"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm16
> > -def SHLri32 : I2A32<"shl", 0xC1, MRM4r >; // R32 <<= imm32
> > +def SHLri16 : I2A8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8
> > +def SHLri32 : I2A8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8
> > def SHLmi8 : I2A8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
> > -def SHLmi16 : I2A16<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm16
> > -def SHLmi32 : I2A32<"shl", 0xC1, MRM4m >; // [mem32] <<= imm32
> > +def SHLmi16 : I2A8 <"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
> > +def SHLmi32 : I2A8 <"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
> >
> > def SHRrCL8 : I2A8 <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
> > def SHRrCL16 : I2A16<"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
> > @@ -476,11 +476,11 @@
> > def SHRmCL32 : I2A32<"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
> >
> > def SHRri8 : I2A8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
> > -def SHRri16 : I2A16<"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm16
> > -def SHRri32 : I2A32<"shr", 0xC1, MRM5r >; // R32 >>= imm32
> > +def SHRri16 : I2A8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8
> > +def SHRri32 : I2A8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8
> > def SHRmi8 : I2A8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
> > -def SHRmi16 : I2A16<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm16
> > -def SHRmi32 : I2A32<"shr", 0xC1, MRM5m >; // [mem32] >>= imm32
> > +def SHRmi16 : I2A8 <"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
> > +def SHRmi32 : I2A8 <"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
> >
> > def SARrCL8 : I2A8 <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
> > def SARrCL16 : I2A16<"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
> > @@ -490,21 +490,21 @@
> > def SARmCL32 : I2A32<"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
> >
> > def SARri8 : I2A8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
> > -def SARri16 : I2A16<"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm16
> > -def SARri32 : I2A32<"sar", 0xC1, MRM7r >; // R32 >>>= imm32
> > +def SARri16 : I2A8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8
> > +def SARri32 : I2A8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8
> > def SARmi8 : I2A8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
> > -def SARmi16 : I2A16<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm16
> > -def SARmi32 : I2A32<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm32
> > +def SARmi16 : I2A8 <"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
> > +def SARmi32 : I2A8 <"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
> >
> > def SHLDrrCL32 : I2A32<"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
> > def SHLDmrCL32 : I2A32<"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
> > -def SHLDrri32 : I2A32<"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
> > -def SHLDmri32 : I2A32<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
> > +def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
> > +def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
> >
> > def SHRDrrCL32 : I2A32<"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
> > def SHRDmrCL32 : I2A32<"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
> > -def SHRDrri32 : I2A32<"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
> > -def SHRDmri32 : I2A32<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
> > +def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
> > +def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
> >
> > // Condition code ops, incl. set if equal/not equal/...
> > def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
> >
> >
> > _______________________________________________
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> > llvm-commits at cs.uiuc.edu
> > http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
>
> -Chris
>
>
-Chris
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