[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp LiveVariables.cpp LiveIntervals.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Thu Feb 26 16:02:15 PST 2004
Changes in directory llvm/lib/CodeGen:
RegAllocLocal.cpp updated: 1.59 -> 1.60
LiveVariables.cpp updated: 1.26 -> 1.27
LiveIntervals.cpp updated: 1.63 -> 1.64
---
Log message:
Uncomment assertions that register# != 0 on calls to
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.
---
Diffs of the changes: (+23 -17)
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.59 llvm/lib/CodeGen/RegAllocLocal.cpp:1.60
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.59 Wed Feb 25 23:21:21 2004
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Thu Feb 26 16:00:20 2004
@@ -542,11 +542,13 @@
// physical register is referenced by the instruction, that it is guaranteed
// to be live-in, or the input is badly hosed.
//
- for (unsigned i = 0; i != MI->getNumOperands(); ++i)
- if (MI->getOperand(i).isUse() &&
- !MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ // here we are looking for only used operands (never def&use)
+ if (!MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
+ }
// If this instruction is the last user of anything in registers, kill the
// value, freeing the register being used, so it doesn't need to be
@@ -573,10 +575,11 @@
// Loop over all of the operands of the instruction, spilling registers that
// are defined, and marking explicit destinations in the PhysRegsUsed map.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
- unsigned Reg = MI->getOperand(i).getReg();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ unsigned Reg = MO.getReg();
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
@@ -586,6 +589,7 @@
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
}
}
+ }
// Loop over the implicit defs, spilling them as well.
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
@@ -606,10 +610,11 @@
// implicit defs and assign them to a register, spilling incoming values if
// we need to scavenge a register.
//
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
- unsigned DestVirtReg = MI->getOperand(i).getReg();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
// If DestVirtReg already has a value, use it.
@@ -618,6 +623,7 @@
markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
}
+ }
// If this instruction defines any registers that are immediately dead,
// kill them now.
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.26 llvm/lib/CodeGen/LiveVariables.cpp:1.27
--- llvm/lib/CodeGen/LiveVariables.cpp:1.26 Thu Feb 19 12:32:29 2004
+++ llvm/lib/CodeGen/LiveVariables.cpp Thu Feb 26 16:00:20 2004
@@ -232,7 +232,7 @@
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isUse() && MO.isRegister()) {
+ if (MO.isUse() && MO.isRegister() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@@ -250,7 +250,7 @@
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isDef() && MO.isRegister()) {
+ if (MO.isDef() && MO.isRegister() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
@@ -325,7 +325,7 @@
// the instruction.
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
- if (MO.isRegister() && MO.isDef() &&
+ if (MO.isRegister() && MO.isDef() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);
Index: llvm/lib/CodeGen/LiveIntervals.cpp
diff -u llvm/lib/CodeGen/LiveIntervals.cpp:1.63 llvm/lib/CodeGen/LiveIntervals.cpp:1.64
--- llvm/lib/CodeGen/LiveIntervals.cpp:1.63 Sun Feb 22 19:01:21 2004
+++ llvm/lib/CodeGen/LiveIntervals.cpp Thu Feb 26 16:00:20 2004
@@ -134,7 +134,7 @@
mii != mie; ) {
for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
const MachineOperand& mop = mii->getOperand(i);
- if (mop.isRegister()) {
+ if (mop.isRegister() && mop.getReg()) {
// replace register with representative register
unsigned reg = rep(mop.getReg());
mii->SetMachineOperandReg(i, reg);
@@ -421,7 +421,7 @@
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
- if (mop.isRegister() && mop.isDef())
+ if (mop.isRegister() && mop.getReg() && mop.isDef())
handleRegisterDef(mbb, mi, mop.getReg());
}
}
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