[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8Instrs.td SparcV8.td
Misha Brukman
brukman at cs.uiuc.edu
Wed Feb 25 15:03:02 PST 2004
Changes in directory llvm/lib/Target/SparcV8:
SparcV8Instrs.td updated: 1.1 -> 1.2
SparcV8.td updated: 1.1 -> 1.2
---
Log message:
Clean up the tablegen descriptions for SparcV8.
---
Diffs of the changes: (+22 -35)
Index: llvm/lib/Target/SparcV8/SparcV8Instrs.td
diff -u llvm/lib/Target/SparcV8/SparcV8Instrs.td:1.1 llvm/lib/Target/SparcV8/SparcV8Instrs.td:1.2
--- llvm/lib/Target/SparcV8/SparcV8Instrs.td:1.1 Wed Feb 25 13:28:19 2004
+++ llvm/lib/Target/SparcV8/SparcV8Instrs.td Wed Feb 25 15:02:21 2004
@@ -1,4 +1,4 @@
-//===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
+//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,40 +7,30 @@
//
//===----------------------------------------------------------------------===//
//
+// This file describes the SparcV8 instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
-class Format<bits<4> val> {
- bits<4> Value = val;
-}
+include "../Target.td"
+include "SparcV8Reg.td"
-// All of the SparcV8 instruction formats, plus a pseudo-instruction format:
-def Pseudo : Format<0>;
-def IForm : Format<1>;
-def BForm : Format<2>;
-def SCForm : Format<3>;
-def DForm : Format<4>;
-def XForm : Format<5>;
-def XLForm : Format<6>;
-def XFXForm : Format<7>;
-def XFLForm : Format<8>;
-def XOForm : Format<9>;
-def AForm : Format<10>;
-def MForm : Format<11>;
-
-class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
- let Namespace = "SparcV8";
-
- let Name = nm;
- bits<6> Opcode = opcd;
- Format Form = f;
- bits<4> FormBits = Form.Value;
-}
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
-// Pseudo-instructions:
-def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
-def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
-def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
-def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
+class InstV8 : Instruction { // SparcV8 instruction baseline
+ field bits<32> Inst;
+
+ let Namespace = "V8";
+
+ bits<2> op;
+ let Inst{31-30} = op; // Top two bits are the 'op' field
+
+ // Bit attributes specific to SparcV8 instructions
+ bit isPasi = 0; // Does this instruction affect an alternate addr space?
+ bit isPrivileged = 0; // Is this a privileged instruction?
+}
+include "SparcV8Instrs_F2.td"
+include "SparcV8Instrs_F3.td"
Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -u llvm/lib/Target/SparcV8/SparcV8.td:1.1 llvm/lib/Target/SparcV8/SparcV8.td:1.2
--- llvm/lib/Target/SparcV8/SparcV8.td:1.1 Wed Feb 25 13:28:19 2004
+++ llvm/lib/Target/SparcV8/SparcV8.td Wed Feb 25 15:02:21 2004
@@ -31,10 +31,7 @@
// According to the Mach-O Runtime ABI, these regs are nonvolatile across
// calls:
- let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
- R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
- F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
- F30, F31, CR2, CR3, CR4];
+ let CalleeSavedRegisters = [];
// Pull in Instruction Info:
let InstructionSet = SparcV8InstrInfo;
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