[llvm-commits] CVS: llvm/lib/Target/SparcV8/Makefile README.txt SparcV8.h SparcV8.td SparcV8CodeEmitter.cpp SparcV8InstrInfo.cpp SparcV8InstrInfo.h SparcV8Instrs.td SparcV8JITInfo.h SparcV8Reg.td SparcV8RegisterInfo.cpp SparcV8RegisterInfo.h SparcV8TargetMachine.cpp SparcV8TargetMachine.h

Brian Gaeke gaeke at cs.uiuc.edu
Wed Feb 25 13:29:02 PST 2004


Changes in directory llvm/lib/Target/SparcV8:

Makefile added (r1.1)
README.txt added (r1.1)
SparcV8.h added (r1.1)
SparcV8.td added (r1.1)
SparcV8CodeEmitter.cpp added (r1.1)
SparcV8InstrInfo.cpp added (r1.1)
SparcV8InstrInfo.h added (r1.1)
SparcV8Instrs.td added (r1.1)
SparcV8JITInfo.h added (r1.1)
SparcV8Reg.td added (r1.1)
SparcV8RegisterInfo.cpp added (r1.1)
SparcV8RegisterInfo.h added (r1.1)
SparcV8TargetMachine.cpp added (r1.1)
SparcV8TargetMachine.h added (r1.1)

---
Log message:

SparcV8 skeleton


---
Diffs of the changes:  (+736 -0)

Index: llvm/lib/Target/SparcV8/Makefile
diff -c /dev/null llvm/lib/Target/SparcV8/Makefile:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/Makefile	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,55 ----
+ ##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
+ # 
+ #                     The LLVM Compiler Infrastructure
+ #
+ # This file was developed by the LLVM research group and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ # 
+ ##===----------------------------------------------------------------------===##
+ LEVEL = ../../..
+ LIBRARYNAME = sparcv8
+ include $(LEVEL)/Makefile.common
+ 
+ # Make sure that tblgen is run, first thing.
+ $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
+                  SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
+                  SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
+ 
+ SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
+                            $(SourceDir)/SparcV8Reg.td \
+                            $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td register names with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
+ 
+ SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
+                            $(SourceDir)/SparcV8Reg.td \
+                            $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td register information header with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
+ 
+ SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
+                          $(SourceDir)/SparcV8Reg.td \
+                          $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td register information implementation with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
+ 
+ SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
+                        $(SourceDir)/SparcV8Instrs.td \
+                        $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td instruction names with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
+ 
+ SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
+                       $(SourceDir)/SparcV8Instrs.td \
+                       $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td instruction information with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
+ 
+ SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
+                           $(SourceDir)/SparcV8Instrs.td \
+                           $(SourceDir)/../Target.td $(TBLGEN)
+ 	@echo "Building SparcV8.td instruction selector with tblgen"
+ 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
+ 
+ clean::
+ 	$(VERB) rm -f *.inc


Index: llvm/lib/Target/SparcV8/README.txt
diff -c /dev/null llvm/lib/Target/SparcV8/README.txt:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/README.txt	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,9 ----
+ 
+ SparcV8 backend skeleton
+ ------------------------
+ 
+ This directory will house a 32-bit SPARC V8 backend employing a expander-based
+ instruction selector.  Watch this space for more news coming soon!
+ 
+ $Date: 2004/02/25 19:28:19 $
+ 


Index: llvm/lib/Target/SparcV8/SparcV8.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8.h:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8.h	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,42 ----
+ //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the entry points for global functions defined in the LLVM
+ // SparcV8 back-end.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef TARGET_SPARCV8_H
+ #define TARGET_SPARCV8_H
+ 
+ #include <iosfwd>
+ 
+ namespace llvm {
+ 
+ class FunctionPass;
+ class TargetMachine;
+ 
+ // Here is where you would define factory methods for sparcv8-specific
+ // passes. For example:
+ // FunctionPass *createSparcV8SimpleInstructionSelector (TargetMachine &TM);
+ // FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
+ //                                            TargetMachine &TM);
+ 
+ } // end namespace llvm;
+ 
+ // Defines symbolic names for SparcV8 registers.  This defines a mapping from
+ // register name to register number.
+ //
+ #include "SparcV8GenRegisterNames.inc"
+ 
+ // Defines symbolic names for the SparcV8 instructions.
+ //
+ #include "SparcV8GenInstrNames.inc"
+ 
+ #endif


Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8.td:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8.td	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,41 ----
+ //===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ // Get the target-independent interfaces which we are implementing...
+ //
+ include "../Target.td"
+ 
+ //===----------------------------------------------------------------------===//
+ // Register File Description
+ //===----------------------------------------------------------------------===//
+ 
+ include "SparcV8Reg.td"
+ include "SparcV8Instrs.td"
+ 
+ def SparcV8InstrInfo : InstrInfo {
+   let PHIInst  = PHI;
+ }
+ 
+ def SparcV8 : Target {
+   // Pointers are 32-bits in size.
+   let PointerType = i32;
+ 
+   // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+   // calls:
+   let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+     R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+     F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+     F30, F31, CR2, CR3, CR4];
+ 
+   // Pull in Instruction Info:
+   let InstructionSet = SparcV8InstrInfo;
+ }


Index: llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,43 ----
+ //===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ // 
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "SparcV8TargetMachine.h"
+ 
+ namespace llvm {
+ 
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
+ /// machine code emitted.  This uses a MachineCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions.  This method should returns true if machine code emission is
+ /// not supported.
+ ///
+ bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+                                                       MachineCodeEmitter &MCE) {
+   return true;
+   // It should go something like this:
+   // PM.add(new Emitter(MCE));  // Machine code emitter pass for SparcV8
+   // Delete machine code for this function after emitting it:
+   // PM.add(createMachineCodeDeleter());
+ }
+ 
+ void *SparcV8JITInfo::getJITStubForFunction(Function *F,
+                                             MachineCodeEmitter &MCE) {
+   assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
+   return 0;
+ }
+ 
+ void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
+   assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
+ }
+ 
+ } // end llvm namespace
+ 


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,42 ----
+ //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "SparcV8InstrInfo.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "SparcV8GenInstrInfo.inc"
+ 
+ namespace llvm {
+ 
+ SparcV8InstrInfo::SparcV8InstrInfo()
+   : TargetInstrInfo(SparcV8Insts,
+                     sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
+ }
+ 
+ // createNOPinstr - returns the target's implementation of NOP, which is
+ // usually a pseudo-instruction, implemented by a degenerate version of
+ // another instruction.
+ //
+ MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
+   return 0;
+ }
+ 
+ /// isNOPinstr - not having a special NOP opcode, we need to know if a given
+ /// instruction is interpreted as an `official' NOP instr, i.e., there may be
+ /// more than one way to `do nothing' but only one canonical way to slack off.
+ //
+ bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
+   return false;
+ }
+ 
+ } // end namespace llvm
+ 


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.h	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,48 ----
+ //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef SPARCV8INSTRUCTIONINFO_H
+ #define SPARCV8INSTRUCTIONINFO_H
+ 
+ #include "llvm/Target/TargetInstrInfo.h"
+ #include "SparcV8RegisterInfo.h"
+ 
+ namespace llvm {
+ 
+ class SparcV8InstrInfo : public TargetInstrInfo {
+   const SparcV8RegisterInfo RI;
+ public:
+   SparcV8InstrInfo();
+ 
+   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
+   /// such, whenever a client has an instance of instruction info, it should
+   /// always be able to get register info as well (through this method).
+   ///
+   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ 
+   /// createNOPinstr - returns the target's implementation of NOP, which is
+   /// usually a pseudo-instruction, implemented by a degenerate version of
+   /// another instruction.
+   ///
+   MachineInstr* createNOPinstr() const;
+ 
+   /// isNOPinstr - not having a special NOP opcode, we need to know if a given
+   /// instruction is interpreted as an `official' NOP instr, i.e., there may be
+   /// more than one way to `do nothing' but only one canonical way to slack off.
+   ///
+   bool isNOPinstr(const MachineInstr &MI) const;
+ };
+ 
+ }
+ 
+ #endif


Index: llvm/lib/Target/SparcV8/SparcV8Instrs.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8Instrs.td:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8Instrs.td	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,46 ----
+ //===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ class Format<bits<4> val> {
+   bits<4> Value = val;
+ }
+ 
+ // All of the SparcV8 instruction formats, plus a pseudo-instruction format:
+ def Pseudo : Format<0>;
+ def IForm : Format<1>;
+ def BForm : Format<2>;
+ def SCForm : Format<3>;
+ def DForm : Format<4>;
+ def XForm : Format<5>;
+ def XLForm : Format<6>;
+ def XFXForm : Format<7>;
+ def XFLForm : Format<8>;
+ def XOForm : Format<9>;
+ def AForm : Format<10>;
+ def MForm : Format<11>;
+ 
+ class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
+   let Namespace = "SparcV8";
+ 
+   let Name = nm;
+   bits<6> Opcode = opcd;
+   Format Form = f;
+   bits<4> FormBits = Form.Value;
+ }
+ 
+ // Pseudo-instructions:
+ def PHI : PPCInst<"PHI", 0, Pseudo>;          // PHI node...
+ def NOP : PPCInst<"NOP", 0, Pseudo>;          // No-op
+ def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
+ def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
+ 
+ 


Index: llvm/lib/Target/SparcV8/SparcV8JITInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8JITInfo.h:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8JITInfo.h	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,49 ----
+ //===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetJITInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef SPARCV8JITINFO_H
+ #define SPARCV8JITINFO_H
+ 
+ #include "llvm/Target/TargetJITInfo.h"
+ 
+ namespace llvm {
+   class TargetMachine;
+   class IntrinsicLowering;
+ 
+   class SparcV8JITInfo : public TargetJITInfo {
+     TargetMachine &TM;
+   public:
+     SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
+ 
+     /// addPassesToJITCompile - Add passes to the specified pass manager to
+     /// implement a fast dynamic compiler for this target.  Return true if this
+     /// is not supported for this target.
+     ///
+     virtual void addPassesToJITCompile(FunctionPassManager &PM);
+     
+     /// replaceMachineCodeForFunction - Make it so that calling the function
+     /// whose machine code is at OLD turns into a call to NEW, perhaps by
+     /// overwriting OLD with a branch to NEW.  This is used for self-modifying
+     /// code.
+     ///
+     virtual void replaceMachineCodeForFunction(void *Old, void *New);
+     
+     /// getJITStubForFunction - Create or return a stub for the specified
+     /// function.  This stub acts just like the specified function, except that
+     /// it allows the "address" of the function to be taken without having to
+     /// generate code for it.
+     virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
+   };
+ }
+ 
+ #endif


Index: llvm/lib/Target/SparcV8/SparcV8Reg.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8Reg.td:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8Reg.td	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,82 ----
+ //===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ class PPCReg : Register {
+   let Namespace = "SparcV8";
+ }
+ 
+ // We identify all our registers with a 5-bit ID, for consistency's sake.
+ 
+ // GPR - One of the 32 32-bit general-purpose registers
+ class GPR<bits<5> num> : PPCReg {
+   field bits<5> Num = num;
+ }
+ 
+ // SPR - One of the 32-bit special-purpose registers
+ class SPR<bits<5> num> : PPCReg {
+   field bits<5> Num = num;
+ }
+ 
+ // FPR - One of the 32 64-bit floating-point registers
+ class FPR<bits<5> num> : PPCReg {
+   field bits<5> Num = num;
+ }
+ 
+ // CR - One of the 8 4-bit condition registers
+ class CR<bits<5> num> : PPCReg {
+   field bits<5> Num = num;
+ }
+ 
+ // General-purpose registers
+ def R0  : GPR< 0>;  def R1  : GPR< 1>;  def R2  : GPR< 2>;  def R3  : GPR< 3>;
+ def R4  : GPR< 4>;  def R5  : GPR< 5>;  def R6  : GPR< 6>;  def R7  : GPR< 7>;
+ def R8  : GPR< 8>;  def R9  : GPR< 9>;  def R10 : GPR<10>;  def R11 : GPR<11>;
+ def R12 : GPR<12>;  def R13 : GPR<13>;  def R14 : GPR<14>;  def R15 : GPR<15>;
+ def R16 : GPR<16>;  def R17 : GPR<17>;  def R18 : GPR<18>;  def R19 : GPR<19>;
+ def R20 : GPR<20>;  def R21 : GPR<21>;  def R22 : GPR<22>;  def R23 : GPR<23>;
+ def R24 : GPR<24>;  def R25 : GPR<25>;  def R26 : GPR<26>;  def R27 : GPR<27>;
+ def R28 : GPR<28>;  def R29 : GPR<29>;  def R30 : GPR<30>;  def R31 : GPR<31>;
+ 
+ // Floating-point registers
+ def F0  : FPR< 0>;  def F1  : FPR< 1>;  def F2  : FPR< 2>;  def F3  : FPR< 3>;
+ def F4  : FPR< 4>;  def F5  : FPR< 5>;  def F6  : FPR< 6>;  def F7  : FPR< 7>;
+ def F8  : FPR< 8>;  def F9  : FPR< 9>;  def F10 : FPR<10>;  def F11 : FPR<11>;
+ def F12 : FPR<12>;  def F13 : FPR<13>;  def F14 : FPR<14>;  def F15 : FPR<15>;
+ def F16 : FPR<16>;  def F17 : FPR<17>;  def F18 : FPR<18>;  def F19 : FPR<19>;
+ def F20 : FPR<20>;  def F21 : FPR<21>;  def F22 : FPR<22>;  def F23 : FPR<23>;
+ def F24 : FPR<24>;  def F25 : FPR<25>;  def F26 : FPR<26>;  def F27 : FPR<27>;
+ def F28 : FPR<28>;  def F29 : FPR<29>;  def F30 : FPR<30>;  def F31 : FPR<31>;
+ 
+ // Condition registers
+ def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
+ def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
+ 
+ // Floating-point status and control register
+ def FPSCR : SPR<0>;
+ // fiXed-point Exception Register? :-)
+ def XER : SPR<1>;
+ // Link register
+ def LR : SPR<2>;
+ // Count register
+ def CTR : SPR<3>;
+ // These are the "time base" registers which are read-only in user mode.
+ def TBL : SPR<4>;
+ def TBU : SPR<5>;
+ 
+ /// Register classes: one for floats and another for non-floats.
+ def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
+   R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
+   R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
+ def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+ 


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,99 ----
+ //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "SparcV8.h"
+ #include "SparcV8RegisterInfo.h"
+ #include "llvm/Type.h"
+ using namespace llvm;
+ 
+ SparcV8RegisterInfo::SparcV8RegisterInfo()
+   : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
+                            SparcV8::ADJCALLSTACKUP) {}
+ 
+ int SparcV8RegisterInfo::storeRegToStackSlot(
+   MachineBasicBlock &MBB,
+   MachineBasicBlock::iterator MBBI,
+   unsigned SrcReg, int FrameIdx,
+   const TargetRegisterClass *RC) const
+ {
+   abort();
+   return -1;
+ }
+ 
+ int SparcV8RegisterInfo::loadRegFromStackSlot(
+   MachineBasicBlock &MBB,
+   MachineBasicBlock::iterator MBBI,
+   unsigned DestReg, int FrameIdx,
+   const TargetRegisterClass *RC) const
+ {
+   abort();
+   return -1;
+ }
+ 
+ int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator MBBI,
+                                       unsigned DestReg, unsigned SrcReg,
+                                       const TargetRegisterClass *RC) const {
+   abort();
+   return -1;
+ }
+ 
+ void SparcV8RegisterInfo::
+ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+                               MachineBasicBlock::iterator I) const {
+   abort();
+ }
+ 
+ void
+ SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
+                                          MachineBasicBlock::iterator II) const {
+   abort();
+ }
+ 
+ void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
+     MachineFunction &MF) const {
+   abort();
+ }
+ 
+ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
+   abort();
+ }
+ 
+ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
+                                        MachineBasicBlock &MBB) const {
+   abort();
+ }
+ 
+ 
+ #include "SparcV8GenRegisterInfo.inc"
+ 
+ const TargetRegisterClass*
+ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
+   switch (Ty->getPrimitiveID()) {
+   case Type::LongTyID:
+   case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
+   default:              assert(0 && "Invalid type to getClass!");
+   case Type::BoolTyID:
+   case Type::SByteTyID:
+   case Type::UByteTyID:
+   case Type::ShortTyID:
+   case Type::UShortTyID:
+   case Type::IntTyID:
+   case Type::UIntTyID:
+   case Type::PointerTyID: return &GPRCInstance;
+     
+   case Type::FloatTyID:
+   case Type::DoubleTyID: return &FPRCInstance;
+   }
+ }
+ 


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,58 ----
+ //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef SPARCV8REGISTERINFO_H
+ #define SPARCV8REGISTERINFO_H
+ 
+ #include "llvm/Target/MRegisterInfo.h"
+ #include "SparcV8GenRegisterInfo.h.inc"
+ 
+ namespace llvm {
+ 
+ class Type;
+ 
+ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
+   SparcV8RegisterInfo();
+   const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+ 
+   /// Code Generation virtual methods...
+   int storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
+ 
+   int loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
+   
+   int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ 		   unsigned DestReg, unsigned SrcReg,
+ 		   const TargetRegisterClass *RC) const;
+ 
+   void eliminateCallFramePseudoInstr(MachineFunction &MF,
+                                      MachineBasicBlock &MBB,
+                                      MachineBasicBlock::iterator I) const;
+ 
+   void eliminateFrameIndex(MachineFunction &MF,
+                            MachineBasicBlock::iterator II) const;
+ 
+   void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
+ 
+   void emitPrologue(MachineFunction &MF) const;
+   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ };
+ 
+ } // end namespace llvm
+ 
+ #endif


Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,61 ----
+ //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ // 
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "SparcV8TargetMachine.h"
+ #include "SparcV8.h"
+ #include "llvm/Module.h"
+ #include "llvm/PassManager.h"
+ #include "llvm/Target/TargetMachineImpls.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/Passes.h"
+ 
+ namespace llvm {
+ 
+ // allocateSparcV8TargetMachine - Allocate and return a subclass of 
+ // TargetMachine that implements the SparcV8 backend.
+ //
+ TargetMachine *allocateSparcV8TargetMachine(const Module &M,
+                                             IntrinsicLowering *IL) {
+   return new SparcV8TargetMachine(M, IL);
+ }
+ 
+ /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
+ ///
+ SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
+                                            IntrinsicLowering *IL)
+   : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
+     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
+ }
+ 
+ /// addPassesToEmitAssembly - Add passes to the specified pass manager
+ /// to implement a static compiler for this target.
+ ///
+ bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
+ 					       std::ostream &Out) {
+   // <insert instruction selector passes here>
+   PM.add(createRegisterAllocator());
+   PM.add(createPrologEpilogCodeInserter());
+   // <insert assembly code output passes here>
+   PM.add(createMachineCodeDeleter());
+   return true; // change to `return false' when this actually works.
+ }
+ 
+ /// addPassesToJITCompile - Add passes to the specified pass manager to
+ /// implement a fast dynamic compiler for this target.
+ ///
+ void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+   // <insert instruction selector passes here>
+   PM.add(createRegisterAllocator());
+   PM.add(createPrologEpilogCodeInserter());
+ }
+ 
+ } // end namespace llvm


Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8TargetMachine.h:1.1
*** /dev/null	Wed Feb 25 13:28:29 2004
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.h	Wed Feb 25 13:28:19 2004
***************
*** 0 ****
--- 1,61 ----
+ //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ // 
+ // This file declares the SparcV8 specific subclass of TargetMachine.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef SPARCV8TARGETMACHINE_H
+ #define SPARCV8TARGETMACHINE_H
+ 
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/TargetFrameInfo.h"
+ #include "llvm/PassManager.h"
+ #include "SparcV8InstrInfo.h"
+ #include "SparcV8JITInfo.h"
+ 
+ namespace llvm {
+ 
+ class IntrinsicLowering;
+ 
+ class SparcV8TargetMachine : public TargetMachine {
+   SparcV8InstrInfo InstrInfo;
+   TargetFrameInfo FrameInfo;
+   SparcV8JITInfo JITInfo;
+ public:
+   SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
+ 
+   virtual const SparcV8InstrInfo     &getInstrInfo() const { return InstrInfo; }
+   virtual const TargetFrameInfo  &getFrameInfo() const { return FrameInfo; }
+   virtual const MRegisterInfo *getRegisterInfo() const {
+     return &InstrInfo.getRegisterInfo();
+   }
+   virtual TargetJITInfo *getJITInfo() {
+     return &JITInfo;
+   }
+ 
+   virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
+   virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
+   virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
+ 
+   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
+   /// actually outputting the machine code and resolving things like the address
+   /// of functions.  This method should returns true if machine code emission is
+   /// not supported.
+   ///
+   virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+                                           MachineCodeEmitter &MCE);
+   
+   virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+ };
+ 
+ } // end namespace llvm
+ 
+ #endif





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